1 October 1999 Compact two-step parallel modified-signed-digit adder/substractor based on binary logic operations using electron-trapping devices
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Abstract
A compact two-step modified-signed-digit arithmetic-logic array processor is proposed. When the reference digits are programmed, both addition and subtraction can be performed by the same binary operations regardless of the sign of the input digits. The optical implementation and experimental demonstration using an electron-trapping device are shown. Each digit is encoded by a single pixel, and no polarization is included. Any combinatorial logic can be easily performed without optoelectronic and electro-optic conversions of the intermediate results. The system is compact, general- purpose, simple to align and has a high signal-to-noise ratio.
© (1999) COPYRIGHT Society of Photo-Optical Instrumentation Engineers (SPIE). Downloading of the abstract is permitted for personal use only.
Guoqiang Li, Feng Qian, Hao Ruan, Liren Liu, "Compact two-step parallel modified-signed-digit adder/substractor based on binary logic operations using electron-trapping devices", Proc. SPIE 3805, Photonic Devices and Algorithms for Computing, (1 October 1999); doi: 10.1117/12.364005; https://doi.org/10.1117/12.364005
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