26 August 1999 Algorithm-agile cryptographic coprocessor based on FPGAs
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Abstract
This contribution describes the design and implementation of an algorithm-agile cryptographic co-processor board. The core of the board is an FPGA which can be dynamically configured with a variety of block ciphers. The FPGA is capable of encrypting data at high speed through an ISA bus interface. The board contains a RAM with a collection of FPGA configuration files. In addition, the algorithms can be added or deleted during operation. The co-processor board also contains other reconfigurable logic and a microprocessor for control functions, and high-speed FIFOs for data storage. We report about the general design, our experiences with this proof-of-concept implementation, and recommendations for future work.
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Christof Paar, Christof Paar, Brendon Richard Chetwynd, Brendon Richard Chetwynd, Thomas J. Connor, Thomas J. Connor, Sheng Yung Deng, Sheng Yung Deng, Stephen J. Marchant, Stephen J. Marchant, } "Algorithm-agile cryptographic coprocessor based on FPGAs", Proc. SPIE 3844, Reconfigurable Technology: FPGAs for Computing and Applications, (26 August 1999); doi: 10.1117/12.359537; https://doi.org/10.1117/12.359537
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