26 August 1999 Fixed-point multiplier evaluation and design with FPGA
Author Affiliations +
The hardware implementation of fixed-point multiplication has become a standard feature in almost all processors and computing systems. Though many researchers have studied various multiplication techniques for ASIC technology, the same techniques may not yield the same performance for FPGA- based multipliers. In this paper, we investigate the costs and speed performances associated with various multiplication techniques implemented on a single XC4010PQ160-5 device. The investigation reveals the significant performance influencing factors for effective design of FPGA-based multipliers. Based on the understanding of the revealed performance influencing factors, we propose a parallel multiplication technique appropriate for FPGA implementations. The implementation results demonstrate that the proposed technique is valid and effective. This paper offers useful references for FPGA-based computing unit designs, and provides an important groundwork for effective design and development of FPGA-based computing systems.
© (1999) COPYRIGHT Society of Photo-Optical Instrumentation Engineers (SPIE). Downloading of the abstract is permitted for personal use only.
William W.H. Yu, William W.H. Yu, Shanzhen Xing, Shanzhen Xing, } "Fixed-point multiplier evaluation and design with FPGA", Proc. SPIE 3844, Reconfigurable Technology: FPGAs for Computing and Applications, (26 August 1999); doi: 10.1117/12.359535; https://doi.org/10.1117/12.359535

Back to Top