26 August 1999 IP validation for FPGAs using Hardware Object Technology(tm)
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Abstract
We introduce in this paper the process of validation applied to digital designs in FPGAs. It allows the designer the ability to test his/her implementation using the real data of the application and providing real results. With such real data, it becomes easier to identify where the error occurs and then to understand it.
© (1999) COPYRIGHT Society of Photo-Optical Instrumentation Engineers (SPIE). Downloading of the abstract is permitted for personal use only.
Steve Casselman, John Schewel, Christophe Beaumont, "IP validation for FPGAs using Hardware Object Technology(tm)", Proc. SPIE 3844, Reconfigurable Technology: FPGAs for Computing and Applications, (26 August 1999); doi: 10.1117/12.359525; https://doi.org/10.1117/12.359525
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