Phase-Shifting Mask (PSM) technology is one of the most practical resolution enhancement technologies for fine patterning using the DUV wavelength (248 nm) without employing a new exposure system. In this paper, we applied phase-edge PSM to 0.13 micrometer logic device and investigated the process latitude depending on the mask issues such as phase error, defect, bias, etc. In manufacturing phase-edge mask, the bias method was applied to layout generation in order to correct pattern displacement caused by space CD difference between shifter and non-shifter region. Also the effects of phase error and phase defect were examined and confirmed by simulation and experimental method. Moreover, in order to achieve more accurate CD control, optimization of trim mask design was performed for reducing linewidth variations during double exposure. With design rules extracted from simulation and experiment, the layout generation of full chip level gate layer was done by EDA software. By double exposure method using KrF scanner with 0.6 NA system, 0.13 micrometer logic gate patterns were printed successfully with good process margin and sub-0.10 micrometer patterns with good profile were resolved, which shows the possibility of further optical extension using phase-edge PSM.