High-K dielectric thin films have been investigated as alternative gate dielectrics. Our results suggest that single-layer sputtered ZrO₂ or HfO₂ thin films deposited directly on Si substrate, without the use of a barrier layer, exhibit excellent electrical and reliability characteristics. Equivalent oxide thickness as thin as 9 angstrom with leakage current of about 10^-2 A/cm² was achieved. This is the lowest EOT value ever reported for ZrO₂ and HfO₂ thin films. Low charge- trapping, high breakdown field, and negligible stress- induced leakage currents have also been obtained.

By ultraclean low-pressure CVD using SiH₄ and GeH₄ gases, high quality Si_1-xGe_x epitaxial growth on Si(100) is achieved. In order to prevent island growth and generation of misfit dislocations in the heterostructure, relatively low deposition temperatures and optimization of the layer thickness are inevitable for the high Ge fractions. Atomically flat surfaces and interfaces for the Si/Si_1-xGe_x/Si heterostructures containing Si_0.8Ge_0.2, Si_0.5Ge_0.5 and Si_0.3Ge_0.7 layers are obtained by deposition at 550, 500 and 450 degrees C, respectively. It is also found that the Si_0.5Ge_0.5-channel pMOSFET has the highest peak field- effect mobility. The deposition rate, the Ge fraction and the in-situ doping characteristics with the B₂H₆ and PH₃ addition are expressed based on the modified Langmuir-type adsorption and reaction scheme, assuming that the reactant gas adsorption/reaction depends on the surface materials. Ultrasmall MOSFETs have been also realized by selective epitaxy of impurity-doped Si_1-xGe_x on the source/drain regions.

This paper will provide an overview of the emerging trends in metal gate solutions for advanced CMOS technology. Performance enhancement in silicon-based CMOS technology through MOSFET scaling has shown some limitations with the current polysilicon gate electrode. Replacing polysilicon gate electrode by metal appears to be promising. However, the choice of the metal gate material depends on its work functions, thermal/chemical stability with surrounding materials, process integration, deposition process, resistivity, and eventually performance, reliability and future scaling. This paper will discuss some of the result published in the literature that address some of these issues and propose future directions. Single mid-gap metal gate approach appears to be simpler from an integration point of view but achieving low MOSFET threshold voltage is a concern. Some channel engineering approaches have been reported to address this issue. Dual metal gate approach with work function similar to n⁺ and p⁺ doped poly-Si appears ideal, although processing complexity could be a hindrance. Also the need for inlaid gate integration could be enhanced because of thermal/chemical stability effects of metal gate electrode with underlying gate dielectric, the inability to etch new materials or to reduce device instability due to film stress as in the conventional approach. The performance improvement of CMOS devices has been estimated with metal gates along with reliability issues.

The objective of this work is to evaluate a well-known low resistance refractory metal silicide such as tungsten silicide (WSi_x) for use as a gate electrode in order to achieve faster switching speed. However, the deposition of a WSi_x film in high aspect ratio trenches is difficult in terms of step coverage as well as adhesion when using a low pressure chemical vapor deposition technique. The deposition canditions need to be carefully tweaked to achieve satisfactory step coverage and film thickness. This paper focuses on the deposition conditions of WSi_x films onto boron doped poly-Si gate material to achieve higher step coverage in the trenches.

This paper describes a new way to suppress the floating body effect (FBE) in SOI MOSFETs, which is applicable to the CMOS structure. The FBE can be suppressed by controlling the potential profile in the lower body region of SOI MOSFETs. The threshold voltage (V_T) of SOI NMOSFETs little depends on drain voltage (V_D) when impact ionization is not significant. V_T is determined by the total body charge. On the contrary, when impact ionization significantly occurs, V_T largely depends on V_D. The accumulation of holes in a floating body raises the body bias, and thus the increase in the body bias determines V_T. From the examination of the influence of a substrate voltage (V_SUB), it is clarified that there is a maximum value of V_SUB (V_SUB,MAX) below which the V_T measured at V_D higher than 1 V does not depend on V_SUB. It is also clarified that the dependence of V_T on V_D can be drastically improved by supplying a V_SUB that is higher than V_SUB,MAX. This means that supplying an adequate V_SUB is effective in suppressing the FBE. Holes accumulated in the NMOS body region are significantly decreased by the V_SUB supply, which is supported by 2D device simulation, and hence the FBE in SOI NMOSFETs is suppressed. Supplying positive V_SUB little affects the PMOSFETs characteristics, except for an increase in V_T. Therefore, this method is useful for the SOI CMOSFET structure.

A sub 0.1 microns channel length vertical MOS transistor was developed for processing with equipment typically utilized for older generation devices. One of the important advantages of vertical MOS transistor technology is that the channel length scaling is not limited by the minimum lithographic resolution. The vertical Ldd processing was also developed to improve the short channel effects. The transistor with channel length below 0.1 micrometers has normal characteristics at room temperature, a > 6V Bvdss, and a transconductance with value as high as in the conventional planar transistor of the same channel length.

Nanometer Schottky-Tunneling MOSFETs which use Schottky contacts at both the source and the drain were fabricated by a novel epitaxial CoSi₂ silicide nanopatterning method. The nanopatterning process which is based on local oxidation of silicide layers, involves two key steps. First, a conventional oxidation mask of 20 nm SiO₂ and 300 nm Si₃N₄ was deposited by plasma enhanced chemical vapor deposition on CoSi₂/Si(100) and patterned by optical lithography and dry etching. Second, rapid thermal oxidation (RTO) was performed in dry oxygen. During RTO, the originally continuous silicide layer is separated near the edge of the nitride mask. Oxide formed on top of the gap and on the surface of the uncovered CoSi₂. Highly uniform gaps as narrow as 50nm between the masked and the unprotected regions of the silicide layer have been fabricated for 20nm thick CoSi₂ layers. N-channel Schottky-Tunneling MOSFETs with epitaxial CoSi₂ Schottky contacts at source and drain were fabricated using this nanopatterning method to make the 100nm gate. The devices show good I-V characteristics at 300K.

A 0.6 micrometers RF BiCMOS technology was developed by the modular integration of a 25 GHz f_T, 35 GHz f_MAX NPN transistor and high-quality passive components into an existing 0.6 micrometers analog CMOS process. The resultant process technology supports low-cost, mixed-signal RF applications up to 2.5 GHz.

A new high performance silicon complementary bipolar technology is introduced. In addition a novel process 'enhancement' technique based on a local oxidation is described and demonstrated and NPN devices with cut-off frequencies up to 45GHz and PNP devices of 20GHz have been fabricate. We propose that the technique we have used will allow specific transistors within a circuit to be optimized, as required.

A high performance of 0.18 micrometers CMOS logic device has been developed with 0.15micrometers transistor and six level interconnects. Multi-level interconnect system consists of conventional process with Al wire and dual damascene process with Cu wire. It is well known that a reduction of interconnect delay time is important as the design rule is scaled. Recently low resistance Cu interconnects and low-k dielectric materials are expected to solve this problem We investigated the interconnect delay time of Cu and Al for the fine metal pitch and the coarse metal pitch, to optimize the interconnect system for 0.18 micrometers design rule generation, 4-level Al interconnects with fine metal pitch are suitable for short distance wiring such as intra-block cell to cell interconnects, whereas 2-level Cu interconnects with coarse metal pitch are used for long distance wiring such as mega-block to block interconnects to achieve high- speed and high-density system LSI devices.

Experiments comparing High-Density Plasma (HDP) CVD oxide for gap-fill with a PECVD oxide/plasma etch process show effects on hot carrier reliability, transistor matching, and transistor 1/f noise. We present results from wafers processed in a 0.35 micrometers CMOS technology with three levels of metal. The results indicate that the HDP process used for gap-fill significantly improves matching and noise characteristics of metal covered devices. Both n and p channel current mirrors show improved matching between metal an no metal coverage with the HDP process. The presence of a HDP oxide film in IMD stack can reduce the mean threshold voltage difference between metal and no metal covered n- MOSFETs from 45 mV to about 4 mV. Likewise, the total integrated noise over the frequency range of 10 Hz-100 kHz of metal covered n-MOSFET is improved by a factor of 1.25 by the HDP gap-fill process. However, the HDP process has resulted in significant degradation of the d.c. hot carrier reliability of n-MOSFETs. These effects may be explained by the large amounts of hydrogen incorporated in the back-end dielectric with the HDP process.

The characterization of nmos transistor mismatch for three different standard CMOS technologies is presented. Different methods for matching parameter extraction have been compared. By studying the correlation of these mismatch parameters, an optimized set has been generated. Using these parameters, mismatch of drain current can be predicted and modeled. The model accuracy has been studied. Finally, by comparing the mismatch model found for crucial parameters and for each technology, the impact of gate oxide thickness on mismatch characteristics has been observed.

Control of boron penetration in surface-channel PMOS devices is critical in order to ensure tight threshold voltage (V_t) distribution. Previous work has focused on studying relatively gross boron-penetration effects, which give rise to large shifts in V_t. In practice, low-voltage CMOS technologies are sensitive to small degradation in PMOS V_t scatter due to the onset of boron penetration. Moreover, the use of rapid thermal annealing can give rise to difficult trade-offs between poly depletion and boron penetration. As both of these effects can influence the PMOS V_t we propose a sensitive, systematic, methodology to distinguish between depletion and penetration effects and illustrate its application in a number of advanced CMOS processes, with oxide thickness ranging from 30-50 angstrom.

The benefits of super steep retrograde channel profiles on MOS transistor performance as reported in the literature have been inconsistent. This inconsistency is in part due to the sensitivity of the performance benefit to the process parameters and integration of the retrograde channel profile. As exhaustive study that integrated and optimized a p-ch arsenic retrograde channel profile transistor into a high performance sub 0.18micrometers transistor CMOS microprocessor process was performed. It was found that the dose and energy of the retrograde channel implant significantly affected the performance improvement obtained. A higher SSRC implant dose, or lower implant energy resulted in higher drive current for a given off current relative to a conventional channel profile control transistor. In addition, the improvement in the transistor linear current was even more significant. At I_DOFF equals 1nA, the I_DS and I_DLIN improvement was approximately 10 percent and 16 percent, respectively. Improvement in transistor drive current also increased at higher drive current. The saturated threshold voltage and Drain Induced Barrier Lowering roll-off with effective channel length were superior for the retrograde channel profile versus the conventional channel profile transistor. Gate oxide reliability with the arsenic doping was also evaluated using Voltage Ramped Dielectric Breakdown (VRDB). It was found that the p-ch gate oxide capacitor VRDB failure rate with the arsenic retrograde channel doping profile was as good or better compared with the conventional phosphorous doped channel profile.

Body bias engineering was investigated in the viewpoints of both device and circuit performance. For reverse body bias to suppress standby power, it was found that there might exist an optimal reverse body bias for minimizing the off- state leakage current. The optimal reverse bias value was found to decrease as the temperature goes down and varies form process to process, and technology generation. It is also found that the reduction in leakage current with reverse body bias is enhanced as the device temperature goes up and diminished as the temperature goes down. For forward body bias to improve the performance, it is found that a forward body bias can suppress short channel effects and improves Vt roll-off. Simulations on performance of typical CMOS logic gates shoed that forward body bias can reduce the gate delay and the improvement is enhanced as the power supply deceases. Power and power delay product will not be improved if forward body bias is applied on the entire circuit. A good strategy is to apply a forward body bias on critical path only to improve speed with minimum power trade-off.

Advanced Ti-Salicide schemes using Si implantation either before or after Ti deposition adversely affected transistor performance through lowering of the device drivability. Device impact was sen in increase of the pMOS series resistance with increasing per-amorphization implant Si implant energy. Likewise, the amount of amorphization and silicidation due to different as-deposited Ti thickness for the implant through metal scheme affected most adversely for the pMOS. This degradation is attributed to the implantation and silicidation induced generation of vacancies and interstitials, resulting in the de-activation and subsequent re-distribution of dopants around the transistor LDD and source/drain regions. Results were shown to conform with TRIM simulation of Si implantation profiles.

We have investigated the influence of ambient and laser energy density on the characteristics of excimer laser crystallized poly-Si films and TFT performance. It was found that poly-Si films crystallized in air showed higher peak position of Raman spectra and larger grain size than those crystallized in vacuum. Excimer laser annealing (ELA) in vacuum made the surface roughness of poly-Si films smaller than that in air. These results show that oxygen plays an important role in grain growth. The investigation of TFT performance with gate length of 0.6 micrometers that is comparable to the grain size of ELA poly-Si films showed that intragrain defects as well as grain size influence the TFT performance.

This paper presents a simple methodology to estimate the impact of inversion layer quantization and polysilicon-gate depletion effects on ultra-thin silicon-dioxide gate dielectric. We have used process and device simulation to determine the physical oxide thickness from the measured capacitance data, and the corresponding effective gate oxide thickness at inversion was computed from the simulation data obtained with an without the quantum mechanical and polysilicon depletion effects. The simulation result indicate that the effective gate oxide thickness is significantly higher than the physically grown oxide thickness due to inversion layer quantization and polysilicon depletion effects. The increase in oxide thickness is strongly dependent on the supply voltage and is more than 0.6 nm at 1 V. We have also measured the gate- leakage current for the same devices with gate oxide thickness less than 3 nm. Our data also show that in order to maintain a leakage current >= 1 A/cm² for 1 V operation, the effective gate oxide thickness must be >= 2.2 nm.

In this paper, we discuss the issues involved in the DC hot carrier lifetime extrapolation of sub 100nm NMOS transistors. We look at device degradation due to hot- carrier injection in NMOS transistors with 20 angstrom and 25 angstrom thermal and nitrided oxide gate dielectrics. Stress conditions such as Vg < Vt, Vg > Vt, Vd equals Vd, and Vg at Isubmax are evaluated. Previously, devices greater than 100nm gate length had highest hot carrier degradation at Vg at Isubmax and 1/Vdd linear extrapolation from accelerated stressing condition to operation condition was able to estate the DC lifetime. However, we show that the conventional extrapolation results in a nonlinear fit for devices with gate length