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1 September 1999 Degradation of PMOS series resistance due to Si implantation for Ti-salicide process
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Abstract
Advanced Ti-Salicide schemes using Si implantation either before or after Ti deposition adversely affected transistor performance through lowering of the device drivability. Device impact was sen in increase of the pMOS series resistance with increasing per-amorphization implant Si implant energy. Likewise, the amount of amorphization and silicidation due to different as-deposited Ti thickness for the implant through metal scheme affected most adversely for the pMOS. This degradation is attributed to the implantation and silicidation induced generation of vacancies and interstitials, resulting in the de-activation and subsequent re-distribution of dopants around the transistor LDD and source/drain regions. Results were shown to conform with TRIM simulation of Si implantation profiles.
© (1999) COPYRIGHT Society of Photo-Optical Instrumentation Engineers (SPIE). Downloading of the abstract is permitted for personal use only.
Eng-Hua Lim, Soh Yun Siah, Chong Wee Lim, Yong Meng Lee, Jia Zhen Zheng, Ravi Sundaresan, and Kin Leong Pey "Degradation of PMOS series resistance due to Si implantation for Ti-salicide process", Proc. SPIE 3881, Microelectronic Device Technology III, (1 September 1999); https://doi.org/10.1117/12.360546
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