This paper describes a new way to suppress the floating body effect (FBE) in SOI MOSFETs, which is applicable to the CMOS structure. The FBE can be suppressed by controlling the potential profile in the lower body region of SOI MOSFETs. The threshold voltage (VT) of SOI NMOSFETs little depends on drain voltage (VD) when impact ionization is not significant. VT is determined by the total body charge. On the contrary, when impact ionization significantly occurs, VT largely depends on VD. The accumulation of holes in a floating body raises the body bias, and thus the increase in the body bias determines VT. From the examination of the influence of a substrate voltage (VSUB), it is clarified that there is a maximum value of VSUB (VSUB,MAX) below which the VT measured at VD higher than 1 V does not depend on VSUB. It is also clarified that the dependence of VT on VD can be drastically improved by supplying a VSUB that is higher than VSUB,MAX. This means that supplying an adequate VSUB is effective in suppressing the FBE. Holes accumulated in the NMOS body region are significantly decreased by the VSUB supply, which is supported by 2D device simulation, and hence the FBE in SOI NMOSFETs is suppressed. Supplying positive VSUB little affects the PMOSFETs characteristics, except for an increase in VT. Therefore, this method is useful for the SOI CMOSFET structure.