Capping layers, cleaning method, and rapid thermal processing temperature on cobalt silicide formation

Dinesh Saigal; Gigi Lai; Lisa Yang; Jingang Su; Ken Ngan; Murali K. Narasimhan; Fusen E. Chen; Ajay Singhal; Dave Lopes; Sean Lian; Wanqing Cao; Kevin Tsai; Patrick Lo; Shih-Ked Lee; James Shih

doi:10.1117/12.360574

11 August 1999 Capping layers, cleaning method, and rapid thermal processing temperature on cobalt silicide formation

Dinesh Saigal, Gigi Lai, Lisa Yang, Jingang Su, Ken Ngan, Murali K. Narasimhan, Fusen E. Chen, Ajay Singhal, Dave Lopes, Sean Lian, Wanqing Cao, Kevin Tsai, Patrick Lo, Shih-Ked Lee, James Shih

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Proceedings Volume 3883, Multilevel Interconnect Technology III; (1999) https://doi.org/10.1117/12.360574
Event: Microelectronic Manufacturing '99, 1999, Santa Clara, CA, United States

Abstract

The effect of some key variables such as rapid thermal processing (RTP) temperature, substrate cleaning method and capping layers, on cobalt silicide formation has been investigated. The in-situ RF sputter etch is found to give a post RTP2 R_sh that is equivalent to a wet cleaned wafer. The temperature transformation curve of cobalt films, analyzed with R_sh data and XRD, reveal the formation of Co₂Si-CoSi-CoSi₂ phases in that order. The transformation curves of TiN capped films match those of blanket cobalt but the Ti capped films show the CoSi phase to be stable over a broader temperature range. There is no effect of dopants on the final cobalt disilicide R_sh values for either the single of polycrystalline substrates. Controlled oxygen leak studies in the RTP ambient reveal that the R_sh after RTP1 is degraded if a capping layer is not present. Electrical test results confirm the need for capping layers. This is indicated by lower R_sh and R_c values on both n+ and p+ junctions and poly structures. Furthermore the electrical results are comparable for Ti and TiN layers used as the cap films although the R_sh/R_c values are in general lower for the TiN capped films. Poly gate length vs R_sh plots show the extendibility of the capped cobalt silicide process to the 0.18 um node.

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Dinesh Saigal, Gigi Lai, Lisa Yang, Jingang Su, Ken Ngan, Murali K. Narasimhan, Fusen E. Chen, Ajay Singhal, Dave Lopes, Sean Lian, Wanqing Cao, Kevin Tsai, Patrick Lo, Shih-Ked Lee, and James Shih "Capping layers, cleaning method, and rapid thermal processing temperature on cobalt silicide formation", Proc. SPIE 3883, Multilevel Interconnect Technology III, (11 August 1999); https://doi.org/10.1117/12.360574

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KEYWORDS

Cobalt

Rhodium

Semiconducting wafers

Tin

Etching

Resistance

Silicon

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