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11 August 1999 Integration of Flowfill and Forcefill for cost-effective via applications
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Abstract
This paper reviews work to integrate FlowfillTM planarizing dielectric with ForcefillTM aluminum plug in a 0.5/0.35 micrometers CMOS design. Work to reduce dielectric cracking by modifying the stress of the IMD material is described. The paper discusses liner choice for the ForcefillTM interconnect and how it can influence lithography accuracy, line resistance and electromigration. The use of via chain resistance as a test to determine the degree of metal hole-fill is described.
© (1999) COPYRIGHT Society of Photo-Optical Instrumentation Engineers (SPIE). Downloading of the abstract is permitted for personal use only.
Werner K. Robl, Juergen Foerster, Uwe Hoeckele, Manfred Frank, David Butler, Paul Rich, and K. Beekmann "Integration of Flowfill and Forcefill for cost-effective via applications", Proc. SPIE 3883, Multilevel Interconnect Technology III, (11 August 1999); https://doi.org/10.1117/12.360573
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