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8 October 1999 Automatic verification of asynchronous circuits using modified STG control graph
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Verifying the correctness of asynchronous sequential circuits is one of the most important tasks in asynchronous design. However, the absence of the global clock and the variation of gate delays in asynchronous circuits make the verification a formidable task. In this paper, a method that can perform efficient timing analysis of gate-level implementation of asynchronous circuits is presented. The method is based on specific behavior given by the Signal Transition Graph (STG). By modifying the STG into the STG control graph, the circuit can be simulated correctly with automatic test generation. The ternary logic is introduced in order to describe the behaviors of gates with bounded inertial delays. The program is written in VHDL. Lastly in this paper, one of the many simulation results to detect hazards is presented.
© (1999) COPYRIGHT Society of Photo-Optical Instrumentation Engineers (SPIE). Downloading of the abstract is permitted for personal use only.
Eddie M.C. Wong and Jie Gong "Automatic verification of asynchronous circuits using modified STG control graph", Proc. SPIE 3893, Design, Characterization, and Packaging for MEMS and Microelectronics, (8 October 1999);


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