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8 October 1999 Development of power accumulation-type SiC MOSFET
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Abstract
A new structure of SiC ACCUFET MOSFET for high power applications have been proposed and analyzed by simulation. The new MOSFET has an n-type ion implanted trench region and a MOS structure consisting of a thin surface layer of epitaxially grown n-type SiC. The current flows through then-type ion implanted region, then via accumulation channel of electrons defined in the epitaxially grown SiC surface layer. The thickness and doping of the n-type surface and p-type base epitaxially grown layers control the channel conditions. At zero gate bias the channel is fully depleted by the built-in fields of SiC p-base layer and the gate electrode resulting in a normally off device with the drain voltage supported by the n-drift region. Moreover, this designed structure fully addresses most of the open issues related to the MOS interface problems, i.e. low channel mobility and high electric field in the gate oxide of the MOS structure. 2D numerical simulations demonstrate that the optimized designed structure can withstand the blocking voltage of more than 1000 V, and a low specific on- resistance. The analytically calculated and simulated result son specific on-resistance of the optimized structure show as low a s 19.3 (Omega) cm2 specific on resistance can achieved with low gate bias of 5V.
© (1999) COPYRIGHT Society of Photo-Optical Instrumentation Engineers (SPIE). Downloading of the abstract is permitted for personal use only.
Handoko Linewih, Sima Dimitrijev, and H. Barry Harrison "Development of power accumulation-type SiC MOSFET", Proc. SPIE 3893, Design, Characterization, and Packaging for MEMS and Microelectronics, (8 October 1999); https://doi.org/10.1117/12.368421
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