The neu-MOS transistor, recently discovered by Shibata and Ohmi in 1991, uses capacitively coupled inputs onto a floating gate. Neu-MOS enables the design of conventional analog and digital integrated circuits with a significant reduction in transistor count. Furthermore, neu-MOS circuit characteristics are relatively insensitive to transistor parameter variations inherent in all MOS fabrication processes. Neu-MOS circuit characteristics depend primarily on the floating gate coupling capacitor ratios. It is also thought that this enhancement in the functionality of the transistor, ie. at the most elemental level in circuits, introduces a degree of flexibility which may lead to the realization of intelligent functions at a system level. This paper extends the neu-MOS paradigm to complementary gallium arsenide based on HIGFET transistors. The design and HSPICE simulation results of a neu-GaAs ripple carry adder are presented, demonstrating the potential for very significant transistor count, area and power dissipation reduction through the use of neu-GaAs in VLSI design. Due to the proprietary nature of complementary GaAs data and SPICE parameters, the simulation result are based on a representative composite parameter set derived from a number of complementary GaAs processes. Preliminary simulations indicate a factor of 4 reduction in gate count, and a factor of over 50 in power dissipation over conventional complementary GaAs. Small gate leakage is shown to be useful in eliminating unwanted charge buildup on the floating gate.