27 April 2000 CMOS receiver array with 100 channels on 1-mm2 chip area based on self-calibrating self-regenerative sense ampliers operating at 200 Mbit/s/channel
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Proceedings Volume 3952, Optoelectronic Interconnects VII; Photonics Packaging and Integration II; (2000) https://doi.org/10.1117/12.384388
Event: Symposium on Integrated Optoelectronics, 2000, San Jose, CA, United States
Abstract
Parallel optical interconnects may become the communication method of choice to achieve future high bandwidth data transfer between chips or MCMs. For this purpose, an integrated CMOS detector approach is favorable at the light- reception side, so Flip-chip of detectors is no longer required. In this paper we present an integrated differential CMOS detector layout which gives a flat frequency response of 0.1A/W with a -3dB bit rate over 450 Mbit/s/ch in standard 0.6(mu) technology. The detector works following the SML-detector principle. Based on this SML-detector we fabricated a dense detector/receiver array consisting of 100 channels on one square mm Si area in 0.6(mu) standard CMOS. The detector area is 50 X 50(mu) 2. The detector signal is amplified and latched by a self-regenerative sense-amplifier, which is self- calibrating for increased array homogeneity and receiver yield. The power consumption per receiver channel is an low as 1.1mW and the received light power at 200Mbit/s is 25.1(mu) W. Measured standard deviation on the output jitter is 96ps. Future CMOS technology will improve the maximum detector/receiver bit-rate as well as the attainable sensitivity.
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Maarten Kuijk, Maarten Kuijk, Daniel Coppee, Daniel Coppee, Jan Genoe, Jan Genoe, Roger A. Vounckx, Roger A. Vounckx, } "CMOS receiver array with 100 channels on 1-mm2 chip area based on self-calibrating self-regenerative sense ampliers operating at 200 Mbit/s/channel", Proc. SPIE 3952, Optoelectronic Interconnects VII; Photonics Packaging and Integration II, (27 April 2000); doi: 10.1117/12.384388; https://doi.org/10.1117/12.384388
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