14 April 2000 Experimental demonstration of real-time image processing using a VLSI analog programmable array processor
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Abstract
This paper describes a full-custom mixed-signal chip which embeds distributed optical signal acquisition, digitally- programmable analog parallel processing, and distributed image memory--cache--on a common silicon substrate. The paper briefly describes the chip architecture and focus mostly on presenting experimental evidence of the chip functionality. Multiscale low-pass and high-pass filtering of gray-scale images, analog edges extraction, image segmentation, thresholded gradient detection, mathematical morphology operations, shortest path detection in a labyrinth, skeletonizing, image reconstruction, several non- linear type image processing tasks like absolute value calculation of gray-scale gradient detection and real-time motion detection in QCIF video sequences are some of the very interesting applications that have been demonstrated as available when using the prototype.
© (2000) COPYRIGHT Society of Photo-Optical Instrumentation Engineers (SPIE). Downloading of the abstract is permitted for personal use only.
Gustavo Linan, Gustavo Linan, Rafael Dominguez-Castro, Rafael Dominguez-Castro, Servando Espejo, Servando Espejo, Elisenda Roca, Elisenda Roca, Peter Foldesy, Peter Foldesy, Angel Rodriguez-Vazquez, Angel Rodriguez-Vazquez, "Experimental demonstration of real-time image processing using a VLSI analog programmable array processor", Proc. SPIE 3962, Applications of Artificial Neural Networks in Image Processing V, (14 April 2000); doi: 10.1117/12.382917; https://doi.org/10.1117/12.382917
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