Parallel architecture for the computation of NURBS surfaces

Montserrat Boo; Javier Diaz Bruguera; Emilio Lopez-Zapata

doi:10.1117/12.375243

29 December 1999 Parallel architecture for the computation of NURBS surfaces

Montserrat Boo, Javier Diaz Bruguera, Emilio Lopez-Zapata

Proceedings Volume 3970, Media Processors 2000; (1999) https://doi.org/10.1117/12.375243
Event: Electronic Imaging, 2000, San Jose, CA, United States

Abstract

B-Splines computation for iterative 3D geometric modeling and graphic animation sessions imply large computational requirements which suggests the utilization of high- performance VLSI architectures. In this paper we describe an architecture for the computation of rational B-Spline surfaces and their derivatives. The architecture is based on the utilization of a highly regular and modular structure, suitable for VLSI implementation, which permits the reconfiguration of the system when no derivatives are required. A new scheduling system permits a fully exploited system in both configuration modes, through the understanding of the parallel structure of the algorithm.

Citation Download Citation

Montserrat Boo, Javier Diaz Bruguera, and Emilio Lopez-Zapata "Parallel architecture for the computation of NURBS surfaces", Proc. SPIE 3970, Media Processors 2000, (29 December 1999); https://doi.org/10.1117/12.375243

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