Paper
29 December 1999 Simultaneous multithreaded processor enhanced for multimedia applications
Friederich Mombers, Michel Thomas
Author Affiliations +
Proceedings Volume 3970, Media Processors 2000; (1999) https://doi.org/10.1117/12.375232
Event: Electronic Imaging, 2000, San Jose, CA, United States
Abstract
The paper proposes a new media processor architecture specifically designed to handle state-of-the-art multimedia encoding and decoding tasks. To achieve this, the architecture efficiently exploit Data-, Instruction- and Thread-Level parallelisms while continuously adapting its computational resources to reach the most appropriate parallelism level among all the concurrent encoding/decoding processes. Looking at the implementation constraints, several critical choices were adopted that solve the interconnection delay problem, lower the cache misses and pipeline stalls effects and reduce register files and memory size by adopting a clustered Simultaneous Multithreaded Architecture. We enhanced the classic model to exploit both Instruction and Data Level Parallelism through vector instructions. The vector extension is well justified for multimedia workload and improves code density, crossbars complexity, register file ports and decoding logic area while it still provides an efficient way to fully exploit a large set of functional units. An MPEG-2 encoding algorithms based on Hybrid Genetic search has been implemented that show the efficiency of the architecture to adapt its resources allocation to better fulfill the application requirements.
© (1999) COPYRIGHT Society of Photo-Optical Instrumentation Engineers (SPIE). Downloading of the abstract is permitted for personal use only.
Friederich Mombers and Michel Thomas "Simultaneous multithreaded processor enhanced for multimedia applications", Proc. SPIE 3970, Media Processors 2000, (29 December 1999); https://doi.org/10.1117/12.375232
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KEYWORDS
Multimedia

Computer programming

Clocks

Motion estimation

Logic

Data storage

Genetics

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