19 April 2000 DSP-based real-time video encoding
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Abstract
This paper describes the implementation of H.263 real-time video encoding on TI TMS320C6X. This series of DSPs utilize a common core based on VelociTITM, the advanced Very Long Instruction Word (VLIW) DSP architecture, which makes them ideal for the high performance embedded multimedia applications. In this paper we discuss in detail the used methodologies to structure video coding algorithm in order to exploit the DSP architecture. In particular, a novel DSP- friendly motion estimation algorithm has been developed to achieve the good trade-off between the coding efficiency and coding complexity. This algorithm plays a key role for the realization of real-time video encoding on DSPs. On the EVM board of this kind of DSP (CPU frequency 167 MHz), we were able to demonstrate the H.263 baseline video encoding, CIF (352 X 288), 1Mbit/s at a speed of about 30 fps. Multimedia applications such as consumer set-top boxes, videophones, videoconferencing, network camera will benefit from this performance.
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Minhua Zhou, Minhua Zhou, Raj Talluri, Raj Talluri, } "DSP-based real-time video encoding", Proc. SPIE 3974, Image and Video Communications and Processing 2000, (19 April 2000); doi: 10.1117/12.382945; https://doi.org/10.1117/12.382945
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