An effective methodology has been utilized at AMD to ensure a reliable lithography step. This methodology is based on short loop test wafers that are scanned for defects by a patterned wafer inspection system. The defects are classified during the initial inspection, and with the classified defect count and results, the lot disposition is then determined. The key requirement is to rapidly obtain information on the various yield-limiting defects, so that these defects can be sourced and then eliminated. It proved possible to capture, classify, and analyze defects that could have lead to yield loss. A WF736 wafer inspection tool was utilized with 'on-the-fly' automatic defect classification (OTF-ADC) capability that segregates defects during the inspection. A wide variety of defects were detected, and the OTF-ADC permitted the separate counting of the critical defects and facilitated both excursion detection and defect analysis. Defects included scumming, surface particles, embedded particles, developer residue, drip, irregular pattern, missing pattern, and other pattern defects. With the classification, more rapid sourcing and elimination was possible. In one example, an excursion was detected which would have been hidden using simple total count inspection. In addition, it proved possible to identify and segregate defects not associated with the litho step.