2 June 2000 Overlay measurement: hidden error
Author Affiliations +
Proceedings Volume 3998, Metrology, Inspection, and Process Control for Microlithography XIV; (2000); doi: 10.1117/12.386496
Event: Microlithography 2000, 2000, Santa Clara, CA, United States
As design rules decrease, tighter tolerances are placed on imaging and overlay. With the SIA National technical roadmap indicating that overlay control will be one of the top challenges facing lithography in the future and achieving the overlay specifications of future products will require greater dependence on accurate prediction of total overlay errors. Contributions to product registration include lens distortions and image alignment. Understanding how these errors effect measurement sampling and modeling of product registration will be key to achieving stricter overlay tolerances. This paper investigates the impact of lens distortions on the accuracy of the modeling. Initial testing is performed using a standard matching test reticle and procedure to determine the raw overlay errors. Corrections from three different measurement scenarios are applied to this data and the resulting residuals analyzed and plotted. The ability to enhance the modeling capability through optimized measurement sampling and location of measurement sites is also evaluated using a 'device feature' SEM measurement routine. The paper concludes with a simulation of feature specific distortion errors, a near future concern.
© (2000) COPYRIGHT Society of Photo-Optical Instrumentation Engineers (SPIE). Downloading of the abstract is permitted for personal use only.
Christopher J. Gould, Francis G. Goodwin, William R. Roberts, "Overlay measurement: hidden error", Proc. SPIE 3998, Metrology, Inspection, and Process Control for Microlithography XIV, (2 June 2000); doi: 10.1117/12.386496; https://doi.org/10.1117/12.386496

Overlay metrology

Scanning electron microscopy



Image registration


Semiconducting wafers


Back to Top