Defect reduction for both process development and line monitoring requires not only capturing the defects, but also determining which are yield limiting, and then systematically eliminating these defects. A methodology has been successfully implemented at VLSI-Phillips providing for defect reduction and monitoring based on automatic defect classification. A wafer inspection tool (WF700 series) with 'on-the-fly' automatic defect classification (OTF-ADC) is utilized to capture and segregate defects of interest during the inspection with no loss in throughput. After determination of which defects have yield impact, the inspection is optimized to capture, classify, and track these defects with separate SPC limits. With the OTF-ADC segregation, the key defects of interest can be separately monitored for excursions. If an excursion is manifest, the corrective action can then be immediately implemented. Various cases are discussed including missing vias, metal bridging, and metal sidewall defects. Yield loss analysis was used for defect prioritization.