23 June 2000 0.12-μm logic process using a 248-nm step-and-scan system
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Abstract
Through the use of an optimized 248 nm optical lithography process and an in-situ resist trimming step developed as part of the gate layer etch, we have been able to fabricate 0.12 micron logic gates with acceptable manufacturing process latitudes. The resist trimming step is performed just prior to etching the SiON anti-reflective coating layer. Because the trimming step is done in-situ as part of the gate etch process, the impact on throughput is minimal. The resist trimming process allows the printing of features larger than the target width, increasing the photolithography process latitude by allowing the process to be run at the most optimal conditions. The trimming step also reduces the line edge roughness which is commonly seen for many chemically amplified photoresists. Photolithography process latitudes with and without trimming are compared for on-wafer dimensions of 0.15 and 0.12 micron. The effect of the trimming step on intrawafer critical dimension control is quantified, and electrical performance of the transistors is presented. The extendibility of this technique for 0.10 micron features is presented. Empirical results are compared to PROLITH simulations, and results of a feasibility study for 193 nm lithography are included.
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Daniel Claire Baker, Daniel Claire Baker, Tammy Zheng, Tammy Zheng, Clifford H. Takemoto, Clifford H. Takemoto, Satyendra S. Sethi, Satyendra S. Sethi, Calvin Gabriel, Calvin Gabriel, Gregory S. Scott, Gregory S. Scott, } "0.12-μm logic process using a 248-nm step-and-scan system", Proc. SPIE 3999, Advances in Resist Technology and Processing XVII, (23 June 2000); doi: 10.1117/12.388313; https://doi.org/10.1117/12.388313
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