As design rules dip below 180 nm, DUV scanners are used at all critical levels with overlay requirements approaching 50 nm. Overlay specifications are typically 30% of critical dimension (CD), 45 nm maximum error for 150 nm geometries, but even non- critical layers at quarter micron may still require a 45 nm overlay for optimum device packing densities. The same photoresist (PR) material employed for patterning and etching thin film layers used to define device structures may also be used as an implant mask. Cost reduction efforts have prompted a detailed evaluation of the practical limits of exclusive utilization of UV6 PR for 180 nm CMOS device processing of 200 mm diameter wafers at SEMATECH. This paper addresses the characterization of UV6 PR relative to ion implant masking in order to discontinue i-line and eliminate mix-and-match lithography processing. Initially, wafers were prepared with incremental UV6 blanket thickness and processed through a range of ion implant operations prior to dry resist stripping by oxygen (02) plasma ashing. ThermaWaveTM optical surface roughness measurements were performed on the resultant bare silicon (Si) surface and compared with a non-implanted control sample for evidence of ion penetration and to determine the required PR mask thickness. Realization of conditions corresponding to the onset of elevated ThermaWaveTM Units (TW) established the parameters for a narrow range investigation of ion projection through UV6. Secondary Ion Mass Spectroscopy (SIMS) ion depth profiling was extensively utilized to specify the energy absorption efficiency of UV6 for each implant species; boron (11B), phosphorus (31P), and arsenic (75As). Residual Gas Analysis (RGA) measurements quantified the outgassing constituent elements detected during ion bombardment. This data assisted the effort to establish the optimum UV6 cure (stabilization/bake) process parameters necessary for particle free ashing. At SEMATECH, 11B, represents the most penetrating (P-well, 160 keV) standard implant operation and 75As, (P3PAPT, anti-punchthrough, 180 keV) represents the standard operation most damaging to photoresist surface topography. Wafers with patterned UV6 PR featuring isolated and dense narrow line structures were inspected with an atomic force microscope (AFM) and verified by Scanning Emission Microscopy (SEM) Based Electron Beam Induced X-ray Spectroscopy following high dose, high current As+ implant bombardment. This technique was implemented to establish the optimum O2 plasma ashing conditions in addition to verifying the UV6 physical feature integrity. This paper identifies the evolution of UV6 PR pertaining to standard PMOS device production. Additionally, electrical data corresponding to 250 nm transistor performance is presented for the direct comparison of i-line (GCATM stepper) vs. UV6 (MicraScanIIITM DUV step and scan). The results of this research enabled the exclusive implementation of UV6 PR in favor of i-line, thereby, eliminating the need for mix-and- match reticle alignments between lithography tools through the course of full flow device manufacturing.