5 July 2000 OPC methodology and implementation to prototyping of small SRAM cells of 0.18-μm node logic gate levels
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Abstract
The evaluation of 'future' SRAM designs often involves aggressive patterning techniques. This is especially true for the prototyping stage of a product because the target 'production' tools are either unavailable or suffer from immature processes. This paper describes an OPC implementation method for 0.18 micrometers technology production of small SRAM cells of logic gate levels. A model based proximity correction has been applied to compensate the pattern distortions encountered in DUV lithography patterning. The first step is to generate a process specific empirical model for OPC simulation. To judge the accuracy of the OPC model, a set of linewidth measurements including linewidth versus pitches and linewidth versus linearity could be used to do a model prediction verification. However, linewidth confirmation is only in 1D. A 2D confirmation is important to ensure the success of OPC because there are lots of irregularly shaped layouts in a random logic device. The validity of OPC model prediction also needs to be verified for low contrast areas in patterning using focus exposure matrices by comparing the printed result to the model simulation. This procedure is very important in pushing chip density. Some experimental result from our approaches are discussed in this paper.
© (2000) COPYRIGHT Society of Photo-Optical Instrumentation Engineers (SPIE). Downloading of the abstract is permitted for personal use only.
Qizhi He, Mi-Chang Chang, Shane R. Palmer, Kayvan Sadra, "OPC methodology and implementation to prototyping of small SRAM cells of 0.18-μm node logic gate levels", Proc. SPIE 4000, Optical Microlithography XIII, (5 July 2000); doi: 10.1117/12.389083; https://doi.org/10.1117/12.389083
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