Wideband digital filter using FPGAs

Raymond P. Escoffier; John C. Webber; Larry R. D'Addario; Charles M. Broadwell

doi:10.1117/12.390403

3 July 2000 Wideband digital filter using FPGAs

Raymond P. Escoffier, John C. Webber, Larry R. D'Addario, Charles M. Broadwell

Proceedings Volume 4015, Radio Telescopes; (2000) https://doi.org/10.1117/12.390403
Event: Astronomical Telescopes and Instrumentation, 2000, Munich, Germany

Abstract

A digital filter being developed by the National Radio Astronomy Observatory (NRAO) for the Atacama Large Millimeter Array (ALMA) is presented here. The filter is designed using field programmable gate array (FPGA) integrated circuits and has an equivalent clock rate of 4 GHz. The ALMA radio astronomy array being developed by the NRAO in cooperation with several European scientific agencies will consist of up to 64 twelve-meter diameter antennas to be used for observing astronomical sources at millimeter and submillimeter wavelengths. This instrument is to observe with bandwidths up to 16 GHz per antenna in eight unbroken RF bands of 2 GHz each. Bandwidth-resolution trade-offs are done in ALMA by providing each of the eight 4-Gsample/s digitizers per antenna with a programmable Finite Impulse Response (FIR) digital filter. The filter can be selected to perform 1/1, 1/2, 1/4, . . ., 1/64 band filtering and sample decimation. In the 1/2 band mode, the filter has the equivalent of 128 tap weight multiplications. Tap weights increase by factors of two to the limit of 2048 tap weights when the filter is programmed to be a 1/32 band low-pass or high-pass filter. The filter is designed to process the output of a four-bit digitizer. The filter utilizes RAM look-up tables for tap weight multiplications. The output of the tap weight multiplications drive an adder tree which has 10-bit precision in the early stages and 7-bit precision in latter stages. Output quantizing of the adder tree output is done in look-up table RAM to 2- bit, 4-level precision. The filter is implemented on a 280-mm, 6-U, Euro card using FPGA ICs running with a system clock rate of 125 MHz.

Citation Download Citation

Raymond P. Escoffier, John C. Webber, Larry R. D'Addario, and Charles M. Broadwell "Wideband digital filter using FPGAs", Proc. SPIE 4015, Radio Telescopes, (3 July 2000); https://doi.org/10.1117/12.390403

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