10 April 2000 New ultrathin 3D integration technique: technological and thermal investigations
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Proceedings Volume 4019, Design, Test, Integration, and Packaging of MEMS/MOEMS; (2000) https://doi.org/10.1117/12.382262
Event: Symposium on Design, Test, Integration, and Packaging of MEMS/MOEMS, 2000, Paris, France
Abstract
A new vertical chip integration is proposed, based on the UTCS concept. It consists in stacking thinned chips on top of a silicon substrate. Lateral and vertical metal interconnections and the thinned chips are embedded in BCB layers. This wafer scale integration technique is presented. Thermal behavior of such stacked structure is also discussed.
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Stephane Pinel, Josiane Tasselli, Antoine Marty, Jean-Pierre Bailbe, Eric Beyne, Rita Van Hoof, Santiago Marco, Sergio Leseduarte, Olivier Vendier, Augustin Coello-Vera, "New ultrathin 3D integration technique: technological and thermal investigations", Proc. SPIE 4019, Design, Test, Integration, and Packaging of MEMS/MOEMS, (10 April 2000); doi: 10.1117/12.382262; https://doi.org/10.1117/12.382262
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