Paper
19 July 2000 Requirements for lithography and mask technology from the standpoint of system LSI business
Keiichi Kawate, Tadahiro Takigawa, Hidemi Ishiuchi, Mineo Goto
Author Affiliations +
Abstract
The SLI business embraces inherent problems in relation to silicon process and design implementation. As the technology becomes more complex and geometries become smaller, shortening TAT and reducing costs become ever more urgent and significant tasks. Efforts are currently being made, particularly in the field of compilable total solutions, to shorten TAT and to re-use modules so as to reduce costs. In the trend towards smaller geometries, TAT and costs related to the mask process are becoming significant factors. It is necessary to optimize the entire prices from design to MDP, mask-making and lithography and thereby improve pattern precision, reduce EB writer shots, achieve greater mask latitude and identify true defects. It will also be necessary to re-use the lithography model during MDP and to use a consistent data hierarchy and a consistent data format.
© (2000) COPYRIGHT Society of Photo-Optical Instrumentation Engineers (SPIE). Downloading of the abstract is permitted for personal use only.
Keiichi Kawate, Tadahiro Takigawa, Hidemi Ishiuchi, and Mineo Goto "Requirements for lithography and mask technology from the standpoint of system LSI business", Proc. SPIE 4066, Photomask and Next-Generation Lithography Mask Technology VII, (19 July 2000); https://doi.org/10.1117/12.392024
Advertisement
Advertisement
RIGHTS & PERMISSIONS
Get copyright permission  Get copyright permission on Copyright Marketplace
KEYWORDS
Photomasks

Laser imaging

Silicon

Lithography

Optical proximity correction

Data modeling

Product engineering

RELATED CONTENT

Rule-based OPC and MPC interaction for implant layers
Proceedings of SPIE (October 23 2015)
Accurate lithography analysis for yield prediction
Proceedings of SPIE (October 30 2007)
Technology interactions on reticle delivery
Proceedings of SPIE (October 17 2008)
Virtual fab flow for wafer topography aware OPC
Proceedings of SPIE (March 10 2010)
Hyper-NA model validation for the 45-nm node
Proceedings of SPIE (March 15 2006)

Back to Top