30 May 2000 VLSI architecture for motion estimation on a single-chip video camera
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Proceedings Volume 4067, Visual Communications and Image Processing 2000; (2000) https://doi.org/10.1117/12.386562
Event: Visual Communications and Image Processing 2000, 2000, Perth, Australia
Abstract
This paper presents a flexible architecture for motion estimation and compensation using a 1D pipelined systolic array. It has been specifically designed to implement the four-step search algorithm but can easily be adapted to a wide range of other reduced-complexity search algorithms. The intention is for the architecture to be incorporated into the digital compression unit of a single-chip video camera, the target application of which is as a device enabling people to communicate using sign-language over a standard phone line. The complete architecture has been implemented as register transfer level VHDL code and its functionality has been verified by simulation. The final VLSI layout will be a combination of synthesized and custom- designed cells.
© (2000) COPYRIGHT Society of Photo-Optical Instrumentation Engineers (SPIE). Downloading of the abstract is permitted for personal use only.
Alexander Roach, Alexander Roach, Alireza Moini, Alireza Moini, } "VLSI architecture for motion estimation on a single-chip video camera", Proc. SPIE 4067, Visual Communications and Image Processing 2000, (30 May 2000); doi: 10.1117/12.386562; https://doi.org/10.1117/12.386562
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