24 May 2000 Motivations for optical interconnects to silicon chips (Abstract Only)
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Proceedings Volume 4089, Optics in Computing 2000; (2000); doi: 10.1117/12.386811
Event: 2000 International Topical Meeting on Optics in Computing (OC2000), 2000, Quebec City, Canada
As silicon chips advance to future generations with higher densities of transistors and faster clock speeds, the problems with electrical interconnects to and on silicon chips become significantly worse. Even the most optimistic scaling models show that scaling the wiring down with the transistors leads to interconnects that do not keep up with the faster transistor speeds. The interconnect scaling problem is arguably even worse for connections off the chip. There are also increasing problems with signal integrity on electrical interconnects as speeds increase, including cross-talk between lines, signal distortion and attenuation, increasing need for voltage isolation, poorer timing of the signals, and generally increasing difficulty of design of the interconnect. There are electrical approaches to dealing with these interconnect problems, including changing architectures to avoid use of long interconnects, improving design tools to optimize the interconnect design more effectively, and improving signaling on electrical lines (such as using equalization). All of these will likely be used. Optics, however, arguably offers the only physical solution to the problem ofthe scaling difficulties of interconnects. Because of its different physics (specifically, the absence of electrical resistance phenomena) it avoids the various common problems of electrical interconnect scaling. It also naturally gives voltage isolation, and avoids most of the other signal integrity problems of electrical wires. Because the optics itself does not need to be redesigned as the clock rate is increased, it may make systems easier to design. Optical interconnects, however, do have their own problems. Especially, optical interconnection is an immature technology, leading to many issues, such as the following. It is impossible to reliably predict cost at the present time. The devices and optical components exist mostly in research laboratories. Integration with silicon is still difficult, though possible. Appropriate optomechanical technology for low-cost, convenient optical assemblies has not been developed. Issues still remain in reducing operating voltage of optoelectronic devices to match future silicon generations. It is not clear whether existing optoelectronic devices can meet the operating environment conditions of silicon circuits (e.g., temperature range) in practice. Receiver circuits with sufficient sensitivity, low enough power, and immunity to digital noise have not been sufficiently tested. There have been relatively few systems experiments to test optical interconnects in realistic conditions. Even the precise applications are unclear. The benefits of on-chip optical interconnects are still debatable (though the arguments for off-chip optical interconnects are relatively strong). This tutorial will examine these various arguments [1] —[4] for limitations on electrical interconnects and possibilities for future optical interconnect technology.
© (2000) COPYRIGHT Society of Photo-Optical Instrumentation Engineers (SPIE). Downloading of the abstract is permitted for personal use only.
David A. B. Miller, "Motivations for optical interconnects to silicon chips (Abstract Only)", Proc. SPIE 4089, Optics in Computing 2000, (24 May 2000); doi: 10.1117/12.386811; https://doi.org/10.1117/12.386811

Optical interconnects


Signal attenuation





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