24 May 2000 Parallel pipeline networking and signal processing with field-programmable gate arrays (FPGAs) and VCSEL-MSM smart pixels
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Proceedings Volume 4089, Optics in Computing 2000; (2000) https://doi.org/10.1117/12.386800
Event: 2000 International Topical Meeting on Optics in Computing (OC2000), 2000, Quebec City, Canada
Abstract
We present a networking and signal processing architecture called Transpar-TR (Translucent Smart Pixel Array-Token- Ring) that utilizes smart pixel technology to perform 2D parallel optical data transfer between digital processing nodes. Transpar-TR moves data through the network in the form of 3D packets (2D spatial and 1D time). By utilizing many spatial parallel channels, Transpar-TR can achieve high throughput, low latency communication between nodes, even with each channel operating at moderate data rates. The 2D array of optical channels is created by an array of smart pixels, each with an optical input and optical output. Each smart pixel consists of two sections, an optical network interface and ALU-based processor with local memory. The optical network interface is responsible for transmitting and receiving optical data packets using a slotted token ring network protocol. The smart pixel array operates as a single-instruction multiple-data processor when processing data. The Transpar-TR network, consisting of networked smart pixel arrays, can perform pipelined parallel processing very efficiently on 2D data structures such as images and video. This paper discusses the Transpar-TR implementation in which each node is the printed circuit board integration of a VCSEL-MSM chip, a transimpedance receiver array chip and an FPGA chip.
© (2000) COPYRIGHT Society of Photo-Optical Instrumentation Engineers (SPIE). Downloading of the abstract is permitted for personal use only.
C. B. Kuznia, C. B. Kuznia, Alexander A. Sawchuk, Alexander A. Sawchuk, Liping Zhang, Liping Zhang, Bogdan Hoanca, Bogdan Hoanca, Sunkwang Hong, Sunkwang Hong, Chris Min, Chris Min, Dhawat E. Pansatiankul, Dhawat E. Pansatiankul, Zahir Y. Alpaslan, Zahir Y. Alpaslan, } "Parallel pipeline networking and signal processing with field-programmable gate arrays (FPGAs) and VCSEL-MSM smart pixels", Proc. SPIE 4089, Optics in Computing 2000, (24 May 2000); doi: 10.1117/12.386800; https://doi.org/10.1117/12.386800
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