24 May 2000 Pushing away the communication bottleneck with optical interconnects in symmetric multiprocessors
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Proceedings Volume 4089, Optics in Computing 2000; (2000) https://doi.org/10.1117/12.386878
Event: 2000 International Topical Meeting on Optics in Computing (OC2000), 2000, Quebec City, Canada
Abstract
We analyze the bandwidth needed for transmitting the addresses in future symmetric multiprocessor machines (SMP), constructed around a shared bus due to the critical obligation to preserve the coherence of the memory hierarchy. We show that an address-transaction bandwidth as high as several hundreds of Gbit/s will be necessary not to slow down the execution of most applications in large SMP's. This communication bandwidth seems incompatible with the operation constraints of shared electrical busses, making necessary the search for other implementations of the address transmission network. We consider the introduction of optical interconnects (OI) in this context. We review several solutions, in the ascending order of complexity of the optical subsystems as one critical issue concerns the degree of sophistication of the optical solutions and their cost. We first consider simple point to point OI's for a SMP chipset. The interest for OI's comes from the low energy consumption and from the possibility, in the future, to integrate several thousands of optical input/outputs per electronic chip. The we consider the implementation of an optical bus that is a multipoint optical line involving more optical functionality. We discuss the possibility of multiple accesses to the bus, and the constraints related to the necessity to maintain the coherence of caches.
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Wissam Hlayhel, Wissam Hlayhel, Jacques H. Collet, Jacques H. Collet, Christine Rochange, Christine Rochange, Daniel Litaize, Daniel Litaize, } "Pushing away the communication bottleneck with optical interconnects in symmetric multiprocessors", Proc. SPIE 4089, Optics in Computing 2000, (24 May 2000); doi: 10.1117/12.386878; https://doi.org/10.1117/12.386878
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