Paper
13 November 2000 Efficient arithmetic implementations based on carry-save representations
Dhananjay S. Phatak, Tom Goff, Israel Koren
Author Affiliations +
Abstract
This paper presents arithmetic implementations which use binary redundant numbers based on carry-save representations. It is well- known that constant-time addition, in which the execution delay is independent of operand length, is feasible only if the result is expressed in a redundant representation. Carry-save based formats are one type of a redundant representation which can lead to highly efficient implementations of arithmetic operations. In this paper, we discuss two specific carry-save formats that lead to particularly efficient realizations. We illustrate these formats, and the 'equal-weight grouping' (EWG) mechanism wherein bits having the same weight are grouped together during an arithmetic operation. This mechanism can reduce the area and delay complexity of an implementation. We present a detailed comparison of implementations based on these two carry-save formats including measurements from VLSI cell layouts. We then illustrate the application of these VLSI cells for multi-operand additions in fast parallel multipliers. Finally, we also indicate the relationship with previous results.
© (2000) COPYRIGHT Society of Photo-Optical Instrumentation Engineers (SPIE). Downloading of the abstract is permitted for personal use only.
Dhananjay S. Phatak, Tom Goff, and Israel Koren "Efficient arithmetic implementations based on carry-save representations", Proc. SPIE 4116, Advanced Signal Processing Algorithms, Architectures, and Implementations X, (13 November 2000); https://doi.org/10.1117/12.406503
Lens.org Logo
CITATIONS
Cited by 1 scholarly publication.
Advertisement
Advertisement
RIGHTS & PERMISSIONS
Get copyright permission  Get copyright permission on Copyright Marketplace
KEYWORDS
Computer programming

Very large scale integration

Binary data

Multiplexers

Logic

Device simulation

Dysprosium

RELATED CONTENT

An Ultra-Fast SBNR Divider
Proceedings of SPIE (May 17 1989)
A VLSI architecture for high performance CABAC encoding
Proceedings of SPIE (June 24 2005)
Arithmetic processor design for the T9000 transputer
Proceedings of SPIE (December 01 1991)
Design And Descriptive Tools For Systolic Architectures
Proceedings of SPIE (November 28 1984)

Back to Top