13 November 2000 Methodology to develop gate networks for redundant digit systems
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Abstract
The design of digital systems that make use of redundant digit sets requires a specific design methodology. These types of systems are frequently used in high-performance arithmetic algorithms. Since more than one output represents the correct result and more than one bit-vector may represent the same output value, there are many possibilities for the system's realization. An important decision involves the selection of the digit codes. This decision impacts the area and delay of the final system. After the digit codes are defined, the number of possible implementations is usually large. This paper presents a design methodology for the implementation of redundant digit systems which allows the creation of an environment for the investigation of design alternatives for such systems. The use of this methodology makes it possible to systematically select digit codes and determine the best design solution. It provides the basis for the implementation of a CAD tool that can assist the designer in the generation of minimal gate networks for redundant digit systems. Besides presenting the methodology we also illustrate its use in the design of some redundant adders, and underline rules that should be followed in order to obtain the best gate networks.
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Alexandre F. Tenca, "Methodology to develop gate networks for redundant digit systems", Proc. SPIE 4116, Advanced Signal Processing Algorithms, Architectures, and Implementations X, (13 November 2000); doi: 10.1117/12.406505; https://doi.org/10.1117/12.406505
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