9 October 2000 Design and implementation of an FPGA-based processor for compressed images
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This paper deals with the implementation of a systolic array architecture in hardware using FPGAs for processing compressed binary images without decompressing them. Specifically, run-length encoding (RLE) is used for compression. Processing images in compressed form provides a significant speedup in the computation. Using a systolic architecture and implementing it in hardware further increases the speed.
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Venkataramanan S. Balakrishnan, Venkataramanan S. Balakrishnan, Hardy Joseph Pottinger, Hardy Joseph Pottinger, Fikret Ercal, Fikret Ercal, Mukesh Agarwal, Mukesh Agarwal, } "Design and implementation of an FPGA-based processor for compressed images", Proc. SPIE 4118, Parallel and Distributed Methods for Image Processing IV, (9 October 2000); doi: 10.1117/12.403594; https://doi.org/10.1117/12.403594

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