As advanced source illumination options become available for production implementation, at the 150 nm and 130 nm technology nodes, non-linear effects are introduced in the design shrink- path. In previous technologies, in particular 250 and 180 nm, partial coherence settings are used as a method to control mono- dimensional CD variations among features with different pitches. Source optimization becomes a function of the design pattern to be imaged and of the OPC applied to this design. The advent of Quadrupole, Quasar and Custom Illumination Apertures enables and enhances the use of Optical Extension (OE) technique to image features down to half of the KrF wavelength, but imposes stringent geometrical restrictions on the design, which are not currently well understood. Our work presents a novel methodology for analyzing effects of source illumination variations on full chip design layouts, extending and generalizing the concept of process window. By combining a powerful full-chip imaging simulator and an illuminator design tool, a very large parameter space of design geometries can be explored. Comparison between the desired and the actually imaged patterns is performed, yielding statistically significant CD errors. The analysis of this very large number of printability data points, covering the whole design pattern, allows the classification of critical geometries, i.e. the portions of the design which are process window limiting. Our methodology not only provides an illumination optimization tool for the lithographer, but above all, highlights the need for manufacturability verification performed early at the physical layout stage of the semiconductor design process. In particular, a design verification application is shown, where progressive linear shrinks of a given layout are matched against optimal image settings. Quantitative analysis of the resulting pattern failure modes provides a direct feedback for the layout designer.