Investigations on the impacts of misalignment in the integration of 0.18-u multilevel interconnect

Teck Jung Tang; Juan Boon Tan; Sajan R. Marokkey; Tae Jong Lee; Alan Cuthbertson

doi:10.1117/12.395716

18 August 2000 Investigations on the impacts of misalignment in the integration of 0.18-μ multilevel interconnect

Teck Jung Tang, Juan Boon Tan, Sajan R. Marokkey, Tae Jong Lee, Alan Cuthbertson

Proceedings Volume 4181, Challenges in Process Integration and Device Technology; (2000) https://doi.org/10.1117/12.395716
Event: Microelectronic Manufacturing, 2000, Santa Clara, CA, United States

Abstract

As technology continues to shrink with tighter design rules, it becomes inevitable for the integrated process to demand a more stringent control over the in-line parameters. For multilevel interconnect, each processing step in the formation of every layer of via plug and metal interconnect impacts the overall performance and yield of the silicon wafer. The control of the process thus becomes even more challenging as more layers of interconnect are required to meet the speed performance and density requirements.

Citation Download Citation

Teck Jung Tang, Juan Boon Tan, Sajan R. Marokkey, Tae Jong Lee, and Alan Cuthbertson "Investigations on the impacts of misalignment in the integration of 0.18-μ multilevel interconnect", Proc. SPIE 4181, Challenges in Process Integration and Device Technology, (18 August 2000); https://doi.org/10.1117/12.395716

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