Memories are especially convenient for defect analysis and yield improvement studies because large portions of a memory die are arrange din a regular array that is connected for external testing in such a manner as to facilitate determination of the physical location of failing memory elements. It is frequently desirable to compare the physical location of failing elements with the location of defects identified with in-line inspection equipment as well as to compare the locations of in-line defects identified on different process layers. This process of comparison is often referred to as creating overlay plots, or frequently just overlays. A practical obstacle to the creation of overlays is that the absolute position of locations on wafers is not accurate in typical inspection equipment with the result there are offsets between the same defect as it propagates between layers and between the reported defect location and resultant location of failing bits on a die.
Tom T. Ho,
"Automated alignment scheme for in-line defect data", Proc. SPIE 4182, Process Control and Diagnostics, (23 August 2000); doi: 10.1117/12.410081; https://doi.org/10.1117/12.410081