Split-Gate Flash Device, the poly-to-poly FN Tunneling for erasing and programming with poly gape, is good structure to eliminate the stacked gate issue of 'over-erase' by additional selected gate which is isolating each memory cell from the bit line. However, the overlay error is more concerned, since they require more accuracy in registrations of P1 to Nitrid and P2 to P1. The registration error, including sampling error, mask error and proximity effect, especially at edge pattern of die, result in the field related low yield because of cell leak issue and cell punch-through. From experiment result, different SERIF design shape, the additional OPC, make different CD performance to improve the different direction of registration error. Mask error and proximity error can contribute overlay shift between cell and box-in-box of overlay monitor frame, so the layer shift addition should be considered those intrinsic error and we add scaling and sampling monitor to avoid the registration error of site to site or wafer to wafer.