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23 August 2000 Special simulator to study metastability
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Metastability has been long documented as a problem in digital systems with asynchronous inputs. This problem has been analyzed in CMOS latches using a 2nd order small signal model. However, uses of a third order model taking into account that the effect of the feedback transistor. While second order models are helpful in understanding how to model the circuit in the region, they do not provide sufficient information to accurately predict the essential parameter (tau) the maximum time at which the circuit may leave the metastable state. The only way to analyze such a circuit is to simulate it, using a simulator that combines small signal and large signal analysis. Future work on metastability will include modeling the feedback transistor as a resistor, and determining whether such a model is a reasonable simplification. The simulator can be modified easily to model small transistor geometries devices and to study the effect of large signal noise, such as ground and power supply bounce, on metastability. The model may also be applied to an interconnect model to improve delay and cross-talk simulations.
© (2000) COPYRIGHT Society of Photo-Optical Instrumentation Engineers (SPIE). Downloading of the abstract is permitted for personal use only.
Mary Sue V. Haydt and Samiha Mourad "Special simulator to study metastability", Proc. SPIE 4182, Process Control and Diagnostics, (23 August 2000);

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