A significant advantage of run-time reconfiguration (RTR) is that circuitry can be minimized or the delay path can be reduced through customization based on the current problem. Two reconfiguration techniques are common in todays applications. These include context switching and constant folding. This paper describes an implementation of a CORDIC processor and show how other reconfiguration techniques, which include run-time routing, can be applied and require low overhead if care is taken. CORDIC is an algorithm to efficiently calculate several different functions in hardware, such as sine and cosine. Through the use of JBits and JRoute the CORDIC processor can be customized to the specific problem, and can be reconfigured at run-time, with minimal changes, to fit another problem. In doing so, the complexity of the circuit is only as complex as it needs to be, and an optimal circuit is maintained. In this paper the CORDIC algorithm and its implementation in an FPGA are described. The implementation is specific to the mode of operation of the CORDIC processor, it is not general purpose. That reduces the complexity of the circuit and RTR can be used to fit the given problem. Also presented is what has been done to reduce the run-time overhead to change between different modes.