20 October 2000 Optimization of the planarizing performance of a DUV organic bottom antireflective coating for via first dual-damascene process: cooperation to achieve material and process characterization
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Proceedings Volume 4226, Microlithographic Techniques in Integrated Circuit Fabrication II; (2000) https://doi.org/10.1117/12.404853
Event: International Symposium on Microelectronics and Assembly, 2000, Singapore, Singapore
Abstract
The work outlines a solution to the challenge of integrating a planarizing BARC into the via first dual damascene manufacturing process. We report the initial problems encountered in attempting the planarizing process and the resulting investigation into the coating process. We identify the critical parameters relating to the via fill performance of the material which relate not only to the process conditions, but also to the chemical make-up of the BARC. As a direct result of this study, a low molecular weight component within the DUV BARC has been identified which may be the key component to planarizing behavior. Cooperation from both supplier and user was necessary, as the availability of alternative test structures, with equivalent topography/surface chemistry, as device wafers was not possible. This resulted in considerable investment [from the user] of sacrificing product wafers for the analysis of the planarizing performance.
© (2000) COPYRIGHT Society of Photo-Optical Instrumentation Engineers (SPIE). Downloading of the abstract is permitted for personal use only.
Paul Williams, Paul Williams, Alice Martin, Alice Martin, Marlene Strobl, Marlene Strobl, William R. Roberts, William R. Roberts, Francis G. Goodwin, Francis G. Goodwin, Lars Voelkel, Lars Voelkel, Axel Feicke, Axel Feicke, Sean Trautman, Sean Trautman, James E. Lamb, James E. Lamb, } "Optimization of the planarizing performance of a DUV organic bottom antireflective coating for via first dual-damascene process: cooperation to achieve material and process characterization", Proc. SPIE 4226, Microlithographic Techniques in Integrated Circuit Fabrication II, (20 October 2000); doi: 10.1117/12.404853; https://doi.org/10.1117/12.404853
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