Advanced integrated process and ESD protection structure to optimize the GOI, HCE, and ESD performance for subquarter micron technology

Jiaw-Ren Shih; J. H. Lee; Huey Liang Hwang

doi:10.1117/12.405370

24 October 2000 Advanced integrated process and ESD protection structure to optimize the GOI, HCE, and ESD performance for subquarter micron technology

Jiaw-Ren Shih, J. H. Lee, Huey Liang Hwang

Author Affiliations +

Proceedings Volume 4227, Advanced Microelectronic Processing Techniques; (2000) https://doi.org/10.1117/12.405370
Event: International Symposium on Microelectronics and Assembly, 2000, Singapore, Singapore

Abstract

In this study, the super-steep retrograde N-channel doping profile was found to degrade the gate oxide integrity (GOI), hot carrier lifetime and the ESD performance. Therefore, a simple method was proposed to from the conventional -channel doping profile without adding the masking step. In addition, to improve the oxide/Si interface quality, a modified LDD structure with As and P₃₁ co-implant followed by gate re-oxidation was also proposed to improve the hot carrier lifetime. To improve the ESD failure threshold, after the real-time I-V characteristics measurement during ESD zapping event and detail failure analysis, a modified multi-finger protection structure with P+ diffusion into source regions was also proposed to relieve the current crowding effect. Moreover, for reducing the snapback voltage, a P- type dopant was proposed to implant into the drain region of the ESD transistor.

Citation Download Citation

Jiaw-Ren Shih, J. H. Lee, and Huey Liang Hwang "Advanced integrated process and ESD protection structure to optimize the GOI, HCE, and ESD performance for subquarter micron technology", Proc. SPIE 4227, Advanced Microelectronic Processing Techniques, (24 October 2000); https://doi.org/10.1117/12.405370

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