This paper presents the modeling of an optical link based on VCSELs. A physics-based model of a VCSEL has been established and validated. The complete optical link has been modeled including free space propagation, Gaussian spatial repartition of light and photodetection. Concerning the photodetection, a low-noise, low-voltage, 2.5Gb/s CMOS photo receiver is being designed, so as to complete the optical link. Furthermore, system parameters such as BER or power consumption can be determined. This results in a fully self-consistent model of a short distance optical interconnection that ca be used to simulate board to board or chip to chip interconnections.

This paper is dealing with design, simulation and test of microsystems. Both existing tools and open research areas are addressed. All through the paper, similarities between the present development of MEMS and the development of microelectronics decades ago are pointed out, including the migration from point tools to Computer-Aided Design frameworks, testing, foundries/fabless business or IP issues. Specific aspects such as thermal simulation of microstructures and thermomechanical design at the package level. The conclusion is depicting a possible global simulation scheme integrating thermomechanical design at the package level. The conclusion is depicting a possible global simulation scheme integrating the needs of Systems on Chip multi language simulation together with the needs of MEMS multipurpose simulation.

Improvements in test technology for next generation microsystems is now becoming essential, especially in sensing applications as in most cases, each sensor has a unique set of characteristics causing inevitable difficulties associated with calibration and validation. Ideally, a microsystem should generate a calibrated output and a reliability indicator. IEEE1451.2 has been developed to provide a standard interface yet research into methods of providing these features through Built-In Self-Test and On- line monitoring techniques is still needed. One of the current industrial techniques uses multiple sensor to determine faults allowing systems to be temporarily reconfigured until the problems are resolved. This technique is only economical if multiple sensors with a strong functional correlation are present within the original system. In case only one sensor is present, using redundancies within this sensor would be more economical than adding extra sensors for test purposes. The aim of this paper is to review generic properties of sensor system to identify areas where mixed signal testing techniques could be adapted for sensor test and to identify areas for further research.

Rectangular micro coils which are used in a wide range of applications are the main components of appropriate wireless transmission systems for frequencies up to 20 MHz. As shown in previous works the self inductance of micro coils has to be maximized to achieve a higher working distance. This can be done by usage of a permeable layer underneath the micro coil. The existing model of the micro coil is extended by use of the magnetic image method to include the inductance yield caused by the permeable layer. The underlying permeable layer or substrate is also modeled accurately to include eddy current phenomena and parasitic elements. To do this the layer respectively the substrate is divided into segments analog to the structure of the micro coil. Each segment is described by lumped elements. All elements are connected together to build up a 3D network which will be used to calculate the terminal impedance. The model and first results will be presented.

Membrane structures are one of the most common elements in microsystems. In order to be able to perform system simulations, behavioral models of their bending lines have to be developed. These models may also be used as a basis for parameter extractions which is a crucial task in the development of microsystems. But parameter extractions can only be performed, if the models used include all of the most important physical effects. Hence, the physical basis of these models has to be very profound.

A simple yet accurate method of modeling the spiral inductor up to six times its first self-resonant frequency is presented. The prosed model, which is derived from the measured data with lumped elements, overcomes the limitation in the valid frequency range of the commonly adopted PI- model and the difficulty in the extraction of element values of broadband model consisting of a number of PI-model cascaded together. Its element values are extracted via systematic data fitting, with two element values to be varied at a time. Such systematic approach offers easy extension of its validity to a higher frequency without complicating the extraction methodology.

This paper presents the latest result on ongoing numerical simulation research of assembly and post-assembly analysis of MEMS devices. Evolving MEMS technologies, including the use of micro-fabricated hinges and gears, have enabled the fabrication of micro-assembled MEMS devices. Examples of these devices include tilting micromirrors, latching mechanisms, and micromotors. A simulation methodology has been developed that allows a MEMS designer to not only model the assembly process, but also to model the effects of various stimuli on the assembled device. Using these capabilities, a MEMS designer can investigate the necessary actuation forces, interfacing mechanisms, and time constraints for micro-assembly, as well as the performance of the device in its assembled state. These simulations rely on multi-stage non-rigid multi-entity contact analysis, dynamic analysis, and large displacement theory. Results are presented for a developed micromirror examples. The assembly process for the 'pop-up' micromirror mechanism are analyzed. After assembly, the coupled electromechanical actuation behavior will be studied. Changes in structural stress, stiffness, natural frequency, and mirror flatness are calculated and show a marked difference from the unstressed/undeformed shape. The newly developed algorithms allow designers to simulate and look into the details of phenomena often ignored in conventional MEMS design. Recent improvements in simulation methodologies allow micro- assembly analyses and post-assembly analyses of the resulting devices. By enabling micro-assembly and post- assembly analyses, we present the first reported MEMS analysis tool capable of modeling the latching mechanisms and post-latching actuation that frequently control current MEMS devices.

The importance of MEMS optimization concerning performance, power consumption, and reliability increases. In the MEMS design flow a variety of specialized tools is available. For simulation on component level FEM tools are widely used. Simulations on system level are carried out with simplified models using simulators like Saber, ELDO or Spice. A few simulators offer tool-specific optimization capabilities but there is a lack of simulator independent support of MEMS optimization. Our approach aims at a flexible combination of simulators and optimization algorithms by partitioning the optimization cycle. This new method is translated into a modular optimization system implemented in JAVA. The paper covers the partitioning of optimization cycle, the interaction between the modules of the optimization system, first experiences in web-based optimization, and the application of the approach to MEMS optimization.

Assembled MEMS structures provide a unique design opportunity by overcoming the inherent planarity of the MEMS fabrication process, allowing for added flexibility and new application areas. However, post-process assembly of these devices is frequently problematic. Force and displacement controls are often imprecise at the microscale resulting in damage to the device. In contrast, self-assembling MEMS structures can avoid external manipulation and therefore can be less likely to suffer damage. Self-assembly, though, requires the added complexity of integrated actuation.

SystemC is a modeling platform consisting of a set of C++ class libraries and a simulation kernel that supports hardware modeling at system, behavioral or register transfer levels. It is platform independent, ANSI C compatible and can be used to establish a design flow that enables and accelerates system-level co-design and IP exchange. If the algorithm is properly mapped into SystemC code, a lot of time can be saved in the conventional design flow, as the hardware description language coding phase is done away with. This paper deals with high level systems design using SystemC modeling. More specifically, it presents a methodology for high level modeling of DSP systems using SystemC and mapping DSP algorithms to SystemC. In order to cater for the existing C based algorithms, a design flow involving conventional C modeling is also presented. The complete front-end design flow can be summarized as below: specifications, conventional C language prototyping, untimed simulation, mapping C to SystemC, timed simulation and synthesis. A typical example of a FIR filter design is taken up to illustrate the SystemC based modeling flow.

Evaluation boards are popular as prototyping platforms in embedded software development. They often are preferred over simulation to avoid modeling effort and simulation times as well as over compete hardware prototypes to avoid development cost. Evaluation boards provide accurate timing results as long as the main architecture parameters match the target hardware system. For larger processors, this is often not the case since the cache and main memory architectures might differ. Another problem is the lack of observability of the software execution. Pin-Out versions of processors with improved observability are expensive and not always available, and on-chip processor test support requires software adaption. A particular problem arises when trying to verify the running time bounds of embedded software such as required for hard real-time systems. Here, formal analysis approaches have been proposed which require segment-wise execution of a program under investigation. Another problem is the accurate analysis of processor power consumption for different execution paths.

With increasing design complexity of digital systems and small device features in sub-micron technologies, interconnection in the digital systems becomes more significant. In this paper, a technique for data path allocation aiming at interconnection optimization is presented. Not only can it optimize the interconnections of the design, but also it enables designers to balance the register cost and interconnection cost. Experimental test results show that this technique can produce good designs.

This paper presents an approach for data path allocation in high-level synthesis aiming at power reduction. In this approach, the register allocation and module allocation are performed in the same phase in polynomial time. The power consumption is reduced by minimizing the functional switching and switched capacitance of the implementation architecture. The experimental results confirm the viability and usefulness of the approach in minimizing power consumption while keeping the number of registers and interconnections to the optimal.

This paper addresses the problem of path constraint satisfaction form delay bound determination. Based on a path delay profiling tool a method is developed to determine the feasibility of delay constraint imposed on circuit path. From the evolution of the path delay profile with transistor sizing conditions, upper and lower bounds of delay are defined and characterized in terms of loading factors. Using these bounds as a reference, a method is developed to define average loading factors and equivalently transistor size allowing to satisfy timing constraint on critical path. Examples of application are given on different ISCAS circuits.

This paper is related to synthesis of concurrently self- testing control units providing pre-defined level of fault coverage. Compaction of test data is one of the core elements of on-line monitoring over control flow execution in terms of its integrity and correctness. Traditionally, the most widely employed compression algorithm is so-called Signature Compression. It is based on the well-established theory on cyclic coding. Cyclic coding and related error correction are very efficient tools when errors lead to inversion of some bits in the initial bit sequence. However, error types and corresponding fault models in case of control unit monitoring are different. Two new fault models for control unit test data are introduced in the paper - shortening and lengthening of the bit sequence being compressed. Results of simulation and comparison of several compression algorithms for these fault models are presented in the paper. The control units of micro-programmed type are considered through out the paper though the results can be applicable to other control unit architectures.

This paper reviews and also discusses some of the important issues in MOSFET Modeling for radio frequency integrated circuits (RFICs). A brief review of some popular or common MOSFET models that can predict the RF properties of MOSFETs is presented. At present, these include BSIM3v3, EKV, MOS Model 9 and adaptations of HSPICE models, and most of them are discussed here. Attention is paid to RF noise parameter extraction and modeling of MOSFETs, since this has been relatively neglected compared to the AC modeling and parameter extraction. Finally, some new and exciting result son the effects of DC electrical stresses on the microwave properties of NMOSFETs, especially the unity current-gain frequencies and maximum oscillation frequencies are presented for different stress times and at different biasing conditions. Modeling of the effects of stress on the RF properties of MOSFETs is still to be investigated.

For long gate-width FET devices, distributed model provides better accuracy. However the extraction of model parameters are difficult as they are expressed in unit gate width which may be different from the device under investigation. In this paper a technique is proposed for defining these model parameters by linking them with lumped element equivalent circuits through simple relations. A good correlation between the lumped and the distributed models are observed for a 2 by 300 micrometers pHEMT device. The method provides initial values of the distributed model, which may further be optimized for perfect fit over wider frequency range.

An accurate modeling of avalanche breakdown of HBTs in compact bipolar transistor models for circuit simulation is presented. Based on various device electrical characteristics that are grouped into three classes, a modified VBIC avalanche multiplication model is proposed. By simply replacing one constant avalanche model parameter with current linear dependence, the new model predicts well broad behaviors of breakdown from weak avalanche up into high injections.

This paper reports a synthesis system for analog circuits using the concept of over-designed circuits. A library is created with basic over-designed circuits. The system developed will automatically and intelligently explore the design space of various circuits configurations to produce an output circuit that matches the specifications as closely as possible. The input specifications are defined in terms of the circuit performances that can be simulated. Multiple- constraints are allowed in the system.

A PSK-demodulator for a bi-directional data transmission in passive telemetric microsystems is presented in this work. These systems, which use the telemetry link for energy and data transmission, are based on identification systems, which use ASK-modulation for both data transfer directions. This leads to problems with a bi-directional data transmission in sensor applications, where the power consumption is significantly higher than in identification systems. A system which uses a PSK to transfer data into the microsystem to improve the energy transfer during data transmission is presented. The key component of this system is a novel PSK-demodulator, which works without an internal oscillator a d therefore no PLL is needed. The major advantages of the presented systems are the self adaptation to the carrier frequency and the independence of the demodulator of parameter drifts.

An automatic gain control (AGC) stage is an essential part of hearing aid circuits. In the CMOS version of micro power hearing aids the AGC stage consists of a variable gain amplifier realized through a differential input stage.

The significant advances in VLSI technology provided the impetus for porting algorithms into architectures. The CORDIC algorithm reigned supreme in this regard due to its canny ability to decimate trigonometric and hyperbolic functions with simple shift and add operations. Despite further refinements of the algorithm with the introduction of redundant arithmetic and higher radix CORDIC techniques, in terms of circuit latency and performance, the iterative nature remains to be the major bottleneck for further optimization. Although several techniques have been prosed to minimize this drawback, a technique known as flat CORDIC aims to eliminate it completely. In flat CORDIC, the conventional X and Y recurrences are successively substituted to express the final vectors in terms of the initial paper, the techniques devised for the VLSI efficient implementation of a 16-bit flat CORDIC based sine-cosine generator are presented. Three schemes for pipelining the 16-bit flat CORDIC design for high throughput solutions have been discussed. The 16-bit architecture has been synthesized using 0.35(mu) CMOS process library. Finally, a detailed comparison with other major contributions show that the flat CORDIC based size-cosine generators are, on an average, 30 percent faster with a significant 30 percent saving in silicon area.

The significant advances in VLSI technology provided the impetus for porting algorithms into architectures. The CORDIC algorithm reigned supreme in this regard due to its canny ability to decimate trigonometric and hyperbolic functions with simple shift and ad operations. Despite further refinements of the algorithm with the introduction of redundant arithmetic and higher radix CORDIC techniques, in terms of circuit latency and performance, the iterative nature remains to be the major bottleneck for further optimization. In this paper, it has been shown that, for Sine/Cosine computations, the iterative process can be avoided during the determination of the polarity of micro- rotations. An efficient pre-computation method for the determination of the pre-computation of the polarity of micro-rotations has been realized by incorporating the Split Decomposition Algorithm. A ROM-less architecture for the pre-computation of the polarity of micro-rotations has been devised after developing a new algorithm that exploits certain properties of the signed digits. The architecture was implemented using VHDL and the functionality simulated netlist has been synthesized with 0.35 (mu) technology library. Finally, a detailed comparison has been made with the help of area-time measures to demonstrate the advantages of precomputing the polarity of micro-rotations.

In this paper an ASIC implementation of a low cost speech recognition system for small vocabulary, 15 isolated word, speaker independent is presented. The IC is a digital block that receives a 12 bit sample with a sampling rate of 11.025 kHz as its input. The IC is running at 10 MHz system clock and targeted at 0.35 micrometers CMOS process. The whole chip, which includes the speech recognition system core, RAM and ROM contains about 61000 gates. The die size is 1.5 mm by 3 mm. The current design had been coded in VHDL for hardware implementation and its functionality is identical with the Matlab simulation. The average speech recognition rate for this IC is 89 percent for 15 isolated words.

With a wide range of student abilities in a class, it is difficult to effectively teach and stimulate all students. A series of web based tutorials was designed to help weaker students and stretch the stronger students. The tutorials consist of a series of HTML web pages with embedded Java applets. This combination is particularly powerful for providing interactive demonstrations because any textual content may be easily provided within the web page. The applet is able to be a compete working program that dynamically illustrates the concept, or provides a working environment for the student to experiment and work through their solution. The applet is dynamic, and responds to the student through both mouse clicks and keyboard entry. These allow the student to adjust parameters, make selections, and affect the way the program is run or information is displayed. Such interaction allows each applet to provide a mini demonstration or experiment to help the student understand a particular concept or technique. The approach taken is illustrated with a tutorial that dynamically shows the relationships between a truth table, Karnaugh amp, logic circuit and Boolean algebra representations of a logic function, and dramatically illustrates the effect of minimization on the resultant circuit. Use of the tutorial has resulted in significant benefits, particularly with weaker students.

Students in the introductory electronics papers work together on a group project in parallel with their regularly scheduled lectures and laboratories. Each team of four students has to design and construct a complex electronic system. The staff involved with the project act as consultants to the design teams. The project is integrative in that it combines together a wide range of tools and techniques form across the spectrum of topics covered in lectures. The system to be designed is split into seven modules, with each module defined explicitly through a set of specifications. For each module, students are required to design a suitable circuit to meet the specifications, verify their design through simulation, prototype their design on breadboard, and realize their design on a PCB. By running the design project in parallel with the theory, the project improves the students understanding of the theory at the same time as developing design skills. An important factor to the success of the project is that the students find it fun.

RF noise in short channel MOSFETs is discussed from the point of view of diffusion and drift current components. It is demonstrated that the access noise is due to a growing contribution of the diffusion current in a short channel device.

xThe definition of effective channel length (L_eff) is different from the metallurgical junction length (L_met), or mask length (L_mask) for lightly-doped-drain (LDD) nMOS devices. Based on the measured data for 0.25 micrometers nMOSFET, an empirical expression on the deviation of effective channel resistance under GCA condition, namely V_DS << V_GS. BY measuring the channel resistance versus different mask lengths under differential variation of gate voltage V_GS, and (Delta) L_eff can be determined. The result predicts that under high gate voltage, a larger portion of gate overlapping region contributes to the conducing effective channel length.

In this paper, a consine-like function instead of a box or a Gaussian-like function is constructed as the pile-up doping in device channel near LDD. The surface potential distribution of nonuniform doping channel is obtained by using Gauss' Law. Threshold voltage roll-up is observed, which is due to the pile-up doping. The simulation results are verified by MEDICI numerical data.

A new parameter extraction methodology - local ratio evaluation is presented which is well suited for converting tone model to another. An example is given for VBIC model extraction by going through Spice Gummel-Poon (SGP) model. It is based on the fact that the VBIC model is a direct enhancement and extension of SGP model. Firstly, the standard SGP model is extracted in the standard way. Then, SGP model parameters are directly converted to VBIC model. Next, local modifications are carried out for those parameters that are affected by different equations used in the two models. Finally, new model parameters for enhanced modeling features are introduced by evaluating the difference between measurement and simulation.

Silicon-on-Insulator (SOI) structures are of great interest for future large scale integrated circuits (LSIs) because parasitic capacitances in devices are reduced. The reduced device capacitances in SOI devices promise a higher speed circuit operation and lower power consumption than the devices fabricate on bulk SI wafers. AN accurate model for the subthreshold current in MOSFET is very important for design of the high speed-low power transistors and circuits for the assessment of the fully depleted SOI technology in comparison to the conventional bulk technology. A new 2D model for subthreshold current in fully depleted silicon-on- insulator metal oxide semi-conductor field effect transistor is developed. The model is based on a 'free inversion areal charge density Qm, solution of 1D effective gate channel equation and a quasi-2D Poisson's equation in weak inversion considering a modified expression for effective channel velocity and phenomenon of velocity overshoot. The mole provides a convenient tool for the design of submicron SOI MOSFETs.

Integration issues involved in incorporating Indium channel implant in nMOSFET device fabrication are studied using TSUPREM4 and MEDICI simulations. This allows a correlation between the channel doping profile and the electrical results. Techniques are aimed at achieving a Steep Retrograde Channel Profile for effective Short Channel Effects and Reverse Short Channel Effects control. One such technique is the inclusion of a Rapid Thermal Anneal step after NLDD implant. Alternative techniques such as Boron pocket removal and NLDD dose reduction are also studied.

Our simulation environment for semiconductor technology analysis is a flexible, user programmable tool for optimization and inverse modeling of semiconductor devices. It is easily customizable through an interactive, object- oriented and functional scripting language. Dynamic load balancing enables to take advantage of a cluster of hosts with minimal requirements on the software infrastructure. Our approach combines the advantages of gradient based and evolutionary algorithm optimizers and the capability of finding global extrema and thus make unattended optimizations without guessing starting values possible.

This paper describes the implementation aspects of a 2D, unstructured grid based Direct Simulation Monte Carlo flow solver for the study of molecular gas dynamics found in thin film deposition processes. A localized data structure base don domain decomposition is developed to improve the particle/molecule tracking, which is otherwise computationally intensive. The method has been implemented on a massively parallel computing platform for shortened simulation time. Results are validated against known analytical solutions and published results. Furthermore, the influence of parameters, such as sticking coefficient and aspect ratio for step coverage on a 1 micrometers wide trench by sputter deposition was studied. The results show that the step coverage deteriorates with increasing sticking coefficient and aspect ratio.

Understanding the origin, the trend and the scale of the relative change of the mechanical strength and the dielectric properties of a nanometric solid is of great importance in designing solid-state device. Here we present a model that describes the nature and behavior of a nanosolid including spherical dots, wires and ultrathin films. Consistency between predictions and experimental observations confirms that the size-driven property-change originates from the chemical bond contraction at surface and the rise in the surface-to-volume ratio of the nanosolid. It is found that the bond contracts by as high as 14 percent and the corresponding Young's modulus increase by 100 percent at surface, and that the dielectric constant of semiconductors decreases with reducing the dimension of the solid, which leads to the blue shift in the photoluminescence and absorption edges.

We present and compare the different design of micromachined silicon condenser microphones. The aim is to develop the microphones with high sensitivity and low fabrication cost. Slotted and corrugated diaphragms have been designed and fabricated in order to increase the mechanical sensitivity of microphones. At the same time we developed the fabrication process for the low stress so stress-free multilayers polysilicon used as the microphone diaphragms. To increase the microphone chip density on one wafer and avoid the sticking problem during the wet release process, a new process design using deep reactive ion etching is prosed, such process system is available in our laboratory.

We present a general model for design and fabrication of high efficient, high brightness IR and visible microchip lasers closely coupling pumped by a fiber coupled diode laser. The design parameters and the output laser characteristics are simulated for both cw and Q-switch operations, as well as their wavelength conversions.

The optimum geometry of the interdigital Metal- Semiconductor-Metal photodetector (MSM-PD) is discussed. From the calculated MSM-PD capacitance and transit time of optically generated carriers, the response time is evaluated and analyzed. We propose a simple design rule for achieving better high-speed response of the MSM-detector. The optimum interelectrode spacing for interdigitized MSM-PD has been established. The potentialities of different semiconductor materials for high-speed MSM-detectors are examined.

This paper describes a methodology to generate behavioral and functional level PLL models. Two sets of PLL block models are derived, one on functional level as a linear PLL and one on behavioral level as a nonlinear PLL. These sets, both containing a voltage controlled oscillator, a phase detector, a frequency divider and reference oscillator, allow for example to build a digital PLL as an RF frequency synthesizer. The models include the most important effects as well as noise in the frequency domain, which influence the behavior of the total PLL. The behavioral model is not valid only for the time domain but also for the frequency domain, which is essential for the characterization of RF blocks.

Recent developments in digital data transport shows that the general trend is moving towards high-speed, low-cost serial networks. Standards such as USB and the relatively new IEEE1394, provide inexpensive, scalable and truly universal I/O connection for virtually any form of digital hardware. Bandwidth requirements for multimedia applications such as real-time digital audio and video, digital broadcasting, wide-band ethernet and the emergence of consumer products such as digital camcorders and VCRs makes data rates of up to 400Mbit/s and beyond, a necessity. In this work we have developed a high-speed high-performance serial bus transceiver, which conforms to the IEEE1394 standards. The HP 0.5micrometers scalable CMOS process available through MOSIS was used for the hardware design. Data rates of up to 800Mbit/s are achieve din comparison to previous similar works that only achieves 300Mbit/s using a BiCMOS process.

A high performance low noise common gate CMOS cascoded transimpedance amplifier designed and simulated in a 0.35 micrometers CMOS technology is presented in this paper. This novel transimpedance amplifier design provides a transimpedance gain of 1k(Omega) with a -3db bandwidth of 2.49GHz, with the input and output noise current spectral density of 7.08pA/(root)Hz and 7.09nV/(root)Hz respectively. With the rapidly emerging optical data-communication technology, this amplifier design is thus well-suited for optical transceiver applications such as the OC-48 standard.

New transparent memory test algorithms for semiconductor memory are presented in the paper along with the modified memory testing simulation package MAP. The test algorithms allow detecting memory read errors - the error type that was not covered in the previous research.

In this paper, a physically based reverse short channel effect (RSCE) threshold voltage compact model is investigated and compared with numerical simulation. A new method to predict RSCE using the compact model is given, which is supported by the TCAD data. A wide range of V_th predictions of nchannel MOSFETs with pile-up structures is conducted. Good prediction results are achieved between the RSCE compact model and TCAD data. The results further support the physics-based RSCE mode, which is useful for both circuit simulation and technology development as well as device design.

This paper presents a multilevel transmission line companion macromodel based on the segmentation modeling for the time domain simulation. The techniques described in this work exploits the characteristic properties of the segmented transmission line model for a more efficient analysis.