24 October 2000 Delay-bound determination for path constraint satisfaction
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Proceedings Volume 4228, Design, Modeling, and Simulation in Microelectronics; (2000) https://doi.org/10.1117/12.405403
Event: International Symposium on Microelectronics and Assembly, 2000, Singapore, Singapore
This paper addresses the problem of path constraint satisfaction form delay bound determination. Based on a path delay profiling tool a method is developed to determine the feasibility of delay constraint imposed on circuit path. From the evolution of the path delay profile with transistor sizing conditions, upper and lower bounds of delay are defined and characterized in terms of loading factors. Using these bounds as a reference, a method is developed to define average loading factors and equivalently transistor size allowing to satisfy timing constraint on critical path. Examples of application are given on different ISCAS circuits.
© (2000) COPYRIGHT Society of Photo-Optical Instrumentation Engineers (SPIE). Downloading of the abstract is permitted for personal use only.
Nadine Azemard, Nadine Azemard, Michel Aline, Michel Aline, Daniel Auvergne, Daniel Auvergne, } "Delay-bound determination for path constraint satisfaction", Proc. SPIE 4228, Design, Modeling, and Simulation in Microelectronics, (24 October 2000); doi: 10.1117/12.405403; https://doi.org/10.1117/12.405403


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