Paper
23 October 2000 Comprehensive methodology for integrated circuit in-line defect classification
Richard L. Guldi, Douglas E. Paradis, Nagarajan Sridhar, Jesse B. Hightower
Author Affiliations +
Proceedings Volume 4229, Microelectronic Yield, Reliability, and Advanced Packaging; (2000) https://doi.org/10.1117/12.404860
Event: International Symposium on Microelectronics and Assembly, 2000, Singapore, Singapore
Abstract
The earliest attempts by human inspectors to classify defects found during in-line inspection of integrated circuits were fraught with difficulties in clarifying defect definitions and in training a diverse and changing inspector staff. These deficiencies were exacerbated by the challenges of expanding classification categories as new defects were discovered. Our diversified product mix had accumulated a knowledge base of approximately seventy defect types, posing a formidable learning challenge for even the most knowledgeable inspector. Not surprisingly, the average accuracy of the group in classifying defects was approximately 55 percent, and even the best inspector scored around 70 percent. To address these issues, we developed a comprehensive methodology for classifying defects. This methodology includes both word descriptions of the physical appearance of defects and a hierarchical questionnaire leading to precise defect classification. After adopting this methodology and implementing strong training programs, our team significantly improved its defect review process, ultimately reaching approximately 80 percent classification accuracy. With this degree of accuracy, we were able to implement defect specific statistical process control charts, together with formalized 'decision tree' procedures for correcting defect excursions. These formalisms then became an effective part of the fab's yield improvement program. Today, as technology advances into the realm of automatic defect classification (ADC), the lessons learned from human defect inspection form a strong foundation by establishing a comprehensive set of defect categories uniquely related to causality and supporting defect identification standards that can be used by the entire community of ADC training engineers.
© (2000) COPYRIGHT Society of Photo-Optical Instrumentation Engineers (SPIE). Downloading of the abstract is permitted for personal use only.
Richard L. Guldi, Douglas E. Paradis, Nagarajan Sridhar, and Jesse B. Hightower "Comprehensive methodology for integrated circuit in-line defect classification", Proc. SPIE 4229, Microelectronic Yield, Reliability, and Advanced Packaging, (23 October 2000); https://doi.org/10.1117/12.404860
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KEYWORDS
Inspection

Etching

Particles

Integrated circuits

Defect inspection

Classification systems

Semiconducting wafers

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