Estimation of the area of voids in deep-submicron aluminium interconnects using resistance-noise measurements

Lip Wei Chu; Kin Leong Pey; Wai Kin Chim; S. K. Loh; E. Er

doi:10.1117/12.404874

23 October 2000 Estimation of the area of voids in deep-submicron aluminium interconnects using resistance-noise measurements

Lip Wei Chu, Kin Leong Pey, Wai Kin Chim, S. K. Loh, E. Er

Author Affiliations +

Proceedings Volume 4229, Microelectronic Yield, Reliability, and Advanced Packaging; (2000) https://doi.org/10.1117/12.404874
Event: International Symposium on Microelectronics and Assembly, 2000, Singapore, Singapore

Abstract

Voids can form in aluminium (Al) interconnects as a result of electro migration, stress migration and process-related problems. Such voids can give rise to reliability issues such as an increase in interconnect resistance that increases the RC delay, and localized stress and heating effects, which further enhance electro migration. In this paper, a novel technique to estimate the effective voids area in deep sub-micron Al lines using combined measurements of resistance fluctuation and low-frequency noise is presented. In the proposed mode, fluctuations in voltage at low frequencies, related to resistance-noise fluctuations in the presence of voids in Al lines, were measured under constant-current biasing condition. The noise measurement is known to be more sensitive to device defects and the presence of voids as compared to the conventional technique of resistance measurement alone. A theoretical model that considers the thermal coefficient of resistance in calculating the change in Al line resistance due to the presence of voids and temperature has been developed to extract the effective void area form the experimental data comprising both 1/f noise and resistance variations.

Citation Download Citation

Lip Wei Chu, Kin Leong Pey, Wai Kin Chim, S. K. Loh, and E. Er "Estimation of the area of voids in deep-submicron aluminium interconnects using resistance-noise measurements", Proc. SPIE 4229, Microelectronic Yield, Reliability, and Advanced Packaging, (23 October 2000); https://doi.org/10.1117/12.404874

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