23 October 2000 System-level I/O power modeling
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Proceedings Volume 4229, Microelectronic Yield, Reliability, and Advanced Packaging; (2000) https://doi.org/10.1117/12.404882
Event: International Symposium on Microelectronics and Assembly, 2000, Singapore, Singapore
Abstract
A methodology is proposed for the electrical characterization of electronic packages in a system-level environment. Modeling and simulation results show the capability of the method by demonstrating both power delivery and I/O signal integrity analysis in a unified environment. In addition to flexibility, the proposed method is capable of achieving accurate results in a fraction of the time as was previously required.
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William P. Pinello, William P. Pinello, P. R. Patel, P. R. Patel, Yuang-Liang Li, Yuang-Liang Li, "System-level I/O power modeling", Proc. SPIE 4229, Microelectronic Yield, Reliability, and Advanced Packaging, (23 October 2000); doi: 10.1117/12.404882; https://doi.org/10.1117/12.404882
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