16 May 2001 2.5-V,1-Gb/s/ch parallel optical receiver in 0.25-μm CMOS technology
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Proceedings Volume 4290, Optoelectronic Integrated Circuits and Packaging V; (2001) https://doi.org/10.1117/12.426917
Event: Symposium on Integrated Optics, 2001, San Jose, CA, United States
Abstract
This paper presents a 1-Gb/s/ch optical receiver with full rail-to-rail output swing designed in a standard 0.25 micrometers CMOS technology. The receiver consists of two parts, the front part is a transimpedance preamplifier which is used to convert the current signal into the voltage signal for the subsequent process, and the end one is a postamplifier which performs the linear and limiting amplification. The voltage data stream, which is converted by the transimpedance preamplifier, is changed into the adjusted digital data stream by comparator which is followed by the preamplifier. During this process, however, it is very critical to suppress the distortion of the data effectively when the input data is regenerated into the adjusted digital ones. For these requirements, our design consideration in this work is as follows. We detected the middle point of the input signal for determining the reference value. The peak detectors determine the positive and negative peak levels of amplitude of the input signal by a comparator with one N-MOS or P-MOS and a capacitator. Then the output voltage signal is divided by the same resistance and its value is decreased in half.
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Sung-Jae Jung, Heung-Soo Kim, Doo-Gun Kim, Young-Wan Choi, "2.5-V,1-Gb/s/ch parallel optical receiver in 0.25-μm CMOS technology", Proc. SPIE 4290, Optoelectronic Integrated Circuits and Packaging V, (16 May 2001); doi: 10.1117/12.426917; https://doi.org/10.1117/12.426917
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