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A key requirement for the development of advanced digital drivers for Low Temperature Poly-Silicon (LTPS) active matrix displays is the provision of a high bandwidth, high resolution Digital to Analogue Converter (DAC) as a prerequisite for higher level integration. For a given panel specification and data rate, the bandwidth and resolution of the conversion process directly influence the efficiency of a digital driver implementation in terms of bezel size, transistor count and power consumption. This paper is concerned with the design and realization of a programmable high performance DAC architecture which meets the requirements for a compact and highly efficient digital data driver. The high performance of the two-stage architecture is achieved by means of a novel pre-charge arrangement that not only increases the speed of operation, but also provides for offset compensation of an analogue buffer with considerably reduced slew rate requirements and power consumption. A switched capacitor implementation of the DAC architecture is presented and the theoretical specifications are verified by simulation. The application of the new architecture to advanced digital drivers with programable input data resolution is briefly discussed.
Michael Brownlow,Graham Cairns,Catherine Dachs,Y. Kubota,H. Washio, andH. Yamashita
"6-bit multiresolution digital-to-analog converter for low-temperature polysilicon digital drivers", Proc. SPIE 4295, Flat Panel Display Technology and Display Metrology II, (30 April 2001); https://doi.org/10.1117/12.424860
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Michael Brownlow, Graham Cairns, Catherine Dachs, Y. Kubota, H. Washio, H. Yamashita, "6-bit multiresolution digital-to-analog converter for low-temperature polysilicon digital drivers," Proc. SPIE 4295, Flat Panel Display Technology and Display Metrology II, (30 April 2001); https://doi.org/10.1117/12.424860