Mosaic imagers increase field of view cost effectively, by connecting single-chip cameras in a coordinated manner equivalent to a large array o9f sensors. Components that would conventionally have been in separate chips can be integrated on the same focal plane by using CMOS image sensors (CIS). Here, a mosaic imaging system is constructed using CIS connected through a bus line which shares common input controls and output(s), and enables additional cameras to be inserted with little system modification. The image- bus consumes relatively low power by employing intelligent power control techniques. However, the bandwidth of the bus will still limit the number of camera modules that can be connected in the mosaic array. Hence, signal-processing components, such as data reduction and encoding, are needed on-chip in order to achieve high readout speed. One such method is described in which the number and sizes of pixel clusters above an intensity threshold are determined using a novel 'object positioning algorithm' architecture. This scheme identifies significant events or objects in the scene before the camera's data are transmitted over the bus, thereby reducing the effective bandwidth. In addition, basic modules in single-chip camera are suggested for efficient data transfer and power control in mosaic imager.